A manufacturing sensitivity analysis of 0.35 μm LDD MOSFET's

Hasnat, K.; Murtaza, S.S.; Tasch, A.F.

doi:10.1109/66.286828

Cited by 10 publications

(3 citation statements)

References 7 publications

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“…A direct application is its utility for roadmap planning, such as for the National Technology Roadmap for Semiconductor (NTRS) (1). It would be particularly valuable in predicting design and operating points that can then be subjected to the more extensive robustness and parameter sensitivity Monte Carlo analyses that are required for manufaeturability studies (2,3). Finally, a simulation tool as envisioned here would be an unprecedented educational aid for CMOS device physics and design.…”

Section: Introductionmentioning

confidence: 99%

An analytical framework for first-order CMOS device design

Alamo¹,

Lynch²,

Antoniadis³

1998

The 1998 International Conference on Characterization and Metrology for ULSI Technology

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We have constructed a simple physics-based analytical framework for MOSFET device simulation. The suite of models is optimized for "well designed" devices that exhibit sufficient electrostatic integrity. This is assessed by means of an analytical model for drain-induced barrier lowering. Using the developed framework, we have simulated 0.1 #m n-channel MOSFETs fabricated at MIT. The agreement obtained between simulations and experiments suggests the viability of this approach in the sub-0.1 #m regime. This analytical framework could form the basis of a compact and efficient first-order CMOS device design environment that could be used to explore key trade-offs and constraints involved in device design several generations ahead. Such a framework could find applications in roadmap planning, sensitivity analysis, and microelectronics education.

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Section: Introductionmentioning

confidence: 99%

An analytical framework for first-order CMOS device design

Alamo¹,

Lynch²,

Antoniadis³

1998

The 1998 International Conference on Characterization and Metrology for ULSI Technology

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show abstract

“…Manuscript received March 9, 1998 Recently TCAD has become one of the key approaches to predict device performance and to optimize process conditions for submicron CMOS development [2]- [4]. In this context, many works have been reported on statistical TCAD, whose approach is indispensable for worst case design of processes for scaled-down CMOS devices.…”

mentioning

confidence: 99%

“…For the practical use of the simulationbased RSM, however, major drawbacks have to be overcome to give reliable predictions. The earlier works fail to describe the TCAD calibration methodology clearly [2]- [4]. TCAD design for process and device design seems to be unsuccessful because of difficulties in achieving the accuracy of simulation and experimental verification.…”

mentioning

confidence: 99%