A new aspect of mechanical stress effects in scaled MOS devices

Hamada, A.; Furusawa, Takeshi; Saito, Naoto; Takeda, Eiji

doi:10.1109/16.75220

Cited by 142 publications

(48 citation statements)

References 7 publications

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“…additional layers on the wafer should not increase the mechanical stress beyond the point where device and interconnect functionality are affected [8][9][10]; the hydrogen passivation in the MOS transistors should not be disrupted, or alternatively be restored at the end of the process (normally by forming a gas anneal around 400 1C) [11].…”

Section: Wafer Post-processingmentioning

confidence: 99%

Adding functionality to microchips by wafer post-processing

Schmitz

2007

Nuclear Instruments and Methods in Physics Research Section A:

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The traditional microchip processes, stores and communicates electrical information. Here we review an emerging class of microchips that have additional functionality through extra integrated components in the chip. In the final manufacturing stage, layers are added on top of the chip, with a specific property such as sensitivity to ionizing radiation. This paper reviews the technology underlying these monolithic microsystems, including the incorporation of new materials, the unconventional application of photoresist layers, and lowtemperature technology for suspended membranes. The manufacturing of exemplary microsystems, such as the active pixel sensor and liquid-crystal-on-silicon, is detailed. A new class of fully integrated radiation imaging systems is now technologically within reach. r

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Section: Wafer Post-processingmentioning

confidence: 99%

Adding functionality to microchips by wafer post-processing

Schmitz

2007

Nuclear Instruments and Methods in Physics Research Section A:

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“…Besides, mechanical strain induced by the silicon nitride (Si 3 N 4 ) capping layer has been reported to influence the performance of short-channel MOSFETs, e.g. gate leakage current and interface trap density, which may compromise reliability [5,6]. Experimental results were reported in our earlier study showing that multi-layer surface micromachining process following conventional CMOS process for post-CMOS processing can lead to performance degradation even for long-channel MOSFETs, such as Vth shift and mobility decrease [7].…”

Section: Introductionmentioning

confidence: 99%

Inter-CMOS process for monolithic integrated MEMS resonator

Zhao

Chen

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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In this work, novel processes for the simultaneous fabrication of the MEMS (micro electro mechanical system) and CMOS (complementary metal oxide semiconductor) components on a monolithic integrated micro-cantilever resonator are proposed. A universal cavity shared by the entire MEMS unit is designed, which decreases the altitude difference between the MEMS and CMOS parts，thus benefiting the subsequent lithography for metal interconnection. The substrate for the CMOS unit is independent on the MEMS unit, assuring electrical isolation. Furthermore, an additional step of selectively removing silicon nitride (Si 3 N 4 ) capping layer and polysilicon (poly-Si) layer upon the CMOS area is added to lower the stress in the MOSFET channel regions. The fabrication of this resonator with on-chip circuits according to the presented inter-CMOS process is investigated first by theoretical analysis, and then moving to experimental verification.

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“…Furthermore, with decrease in the size of modern semiconductor devices, the strain field in the semiconductor devices tends to be strongly influenced by layout design parameters such as the channel length and the geometry of the source and drain regions. 5,6 Therefore, for next-generation technology, it is required to monitor the layout-dependent strain behavior with high precision at nanometer-scale spatial resolutions. Although various tools have been applied to the measurement of strain fields in semiconductor structures, 4,[7][8][9][10][11][12][13][14][15][16][17] there have been relatively few experimental results regarding studying the effect of the channel length on the strain field induced in semiconductor device structures.…”

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confidence: 99%

Channel-Length-Dependence of Strain Field in Transistor Studied via Scanning Moire Fringe Imaging

Kim

Lee

Oshima

et al. 2013

ECS Solid State Letters

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We have applied scanning moiré fringe (SMF) imaging to the quantitative measurement of the strain introduced in n-type channel transistors with embedded SiC in the source and drain. The tensile strain parallel to the channels was reveal with a nano-meter scale spatial resolution. We investigated the strain field in transistors with various channel lengths scaled down to 25 nm, and found that the strain increases up to 0.7% as the channel length shrinks to 35 nm. However, the strain in the channel decreases to 0. 55% as the channel length is scaled from 35 nm down to 25 nm. Strain engineering is routinely applied in the fabrication of advanced semiconductor devices to enhance the mobility of the carriers in transistors.1,2 The mobility of electrons or holes is boosted when the channel in a transistor is under either a tensile or compressive strain, respectively. The Si 1−x C x embedded in the source/drain region has been used for n-type field effect transistors.3 The lattice parameter of Si 1−x C x with a carbon concentration of about 1% is smaller than that of pure Si. Thus, a compressive stress is formed in the source/drain region, which in turn induces a tensile strain in the n-type channel. 4 Since the electrical performance of the device is greatly influenced by the strain field induced in the channel region, it is required to control the strain field for optimum manufacturing processing. Furthermore, with decrease in the size of modern semiconductor devices, the strain field in the semiconductor devices tends to be strongly influenced by layout design parameters such as the channel length and the geometry of the source and drain regions. 5,6 Therefore, for next-generation technology, it is required to monitor the layout-dependent strain behavior with high precision at nanometer-scale spatial resolutions. Although various tools have been applied to the measurement of strain fields in semiconductor structures, 4,7-17 there have been relatively few experimental results regarding studying the effect of the channel length on the strain field induced in semiconductor device structures. 18In this study, we have applied scanning moiré fringe (SMF) imaging, 19 which is a high-angle annular dark-field scanning transmission electron microscope (HAADF-STEM)-based technique, to quantitatively measure the strain field in transistors with various channel lengths down to 25 nm. SMF imaging is a recently developed method that can measure strain fields at a high spatial resolution in the nanometer scale. [20][21][22] In the HAADF-STEM experiment, the SMFs appear when the scanning grating size d s is close to the crystal lattice spacing d l . Figure 1a shows the strained lattice spacing d l that increases from the bottom to the top of the pattern. Figure 1b Fig. 1c. 22 Because the SMF spacing d SMF changes very sensitively to the variation in the lattice plane spacing d l , the strain field can be obtained by substituting the measured d SMF and a calibrated value of d s in the formula for the width of the translational moiré ...

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A new aspect of mechanical stress effects in scaled MOS devices

Cited by 142 publications

References 7 publications

Adding functionality to microchips by wafer post-processing

Adding functionality to microchips by wafer post-processing

Inter-CMOS process for monolithic integrated MEMS resonator

Channel-Length-Dependence of Strain Field in Transistor Studied via Scanning Moire Fringe Imaging

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