A scaling scheme for interconnect in deep-submicron processes

Rahmat, K.; Nakagawa, O.S.; Oh, Soo‐Young; Moll, J.L.; Lynch, William T.

doi:10.1109/iedm.1995.499188

Cited by 46 publications

(15 citation statements)

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“…With interconnect swing potential reduced, the ideal improvement of power consumption and delay for each technology node are shown in Table 3, where V dd ðV t Þ is assumed to be 1.8 V (0.50 V), 1.5 V (0.45 V), 1.2 V (0.40 V), 1.0 V (0.35 V) and 0.7 V (0.25 V) for 0.18, 0.13, 0.10, 0.07 and 0.05 lm technology nodes, respectively [13]. The V dd ðV t Þ values of 0.05 lm technology node come from the reliable deduction based on ITRS 1999.…”

Section: Low Swing Interconnect Designmentioning

confidence: 99%

Study of swing potential on deep submicron on-chip interconnect

Yang

2004

Microelectronics Reliability

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Section: Low Swing Interconnect Designmentioning

confidence: 99%

Study of swing potential on deep submicron on-chip interconnect

Yang

2004

Microelectronics Reliability

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“…For circuit simulation, a 0.25 m SPICE device model was created based on SIA roadmap specifications [19], [20] and typical values reported in the literature. The sensitivity of , the measured drain current when both the gate and drain are held at the supply rail, is shown in Fig.…”

Section: Simulation Examplementioning

confidence: 99%

Simulating the impact of pattern-dependent poly-CD variation on circuit performance

Stine

Boning

Chung

et al. 1998

IEEE Trans. Semicond. Manufact.

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“…Hence, the combined effects of chip size growth and scaling results in the rapid increase of capacitance and resistance of interconnect wires. This increases the propagation delay through interconnects by a factor of S 2 S 2 C , where S is the scaling factor and S C is the chip size increase factor which accounts for the increase in chip size from one generation of ICs to the next [Rahmat et al 1995].…”

Section: Introductionmentioning

confidence: 99%

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

Hanchate

Ranganathan

2004

ACM Trans. Des. Autom. Electron. Syst.

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The continuous scaling of interconnect wires in deep submicron (DSM) circuits results in increased interconnect delay, power, and crosstalk noise. In this work, we develop a game-theoretic framework and multimetric optimization algorithms for the simultaneous optimization during wire sizing of (i) interconnect delay and crosstalk noise, and (ii) interconnect delay, power, and crosstalk noise. We formulate the wire sizing optimization problem as a normal form-game model and solve it using Nash equilibrium theory. Game theory allows the optimization of multiple metrics with conflicting objectives. This property is exploited in modeling the wire sizing problem while simultaneously optimizing various design parameters like interconnect delay, power, and crosstalk noise, which are conflicting in nature. The nets connecting the driving cell and the driven cell are divided into net segments. The net segments within a channel are modeled as players and the range of possible wire sizes forms the set of strategies. The payoff function is modeled (i) as the geometric mean of interconnect delay and crosstalk noise in the case of first formulation, and (ii) as the weighted sum of interconnect delay, power, and crosstalk noise in the second formulation. The net segments are optimized from the ones closest to the driven cell towards the ones at the driving cell. Complete information about the coupling effects among the nets is extracted after the detailed routing phase. The time and space complexities of the proposed wire sizing formulations are linear in terms of the number of net segments. Experimental results on several medium and large opencore designs indicate that the proposed algorithm for simultaneous optimization of interconnect delay and crosstalk noise yields an average reduction of 21.48% in interconnect delay and a 26.25% reduction in crosstalk noise without any area overhead, over and above the optimization from the Cadence place and route tools. It is shown through experimental results that the algorithm performs significantly better than simulated annealing and genetic search. Further, new simple but accurate models are developed for three parallel interconnect net segments. It is shown that these models yield the same level of accuracy with significantly better run times compared to the models reported in Chen et al. [2004]. A mathematical proof of existence for the Nash equilibrium solution for the proposed wire sizing formulation is also provided.

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A scaling scheme for interconnect in deep-submicron processes

Cited by 46 publications

References 1 publication

Study of swing potential on deep submicron on-chip interconnect

Study of swing potential on deep submicron on-chip interconnect

Simulating the impact of pattern-dependent poly-CD variation on circuit performance

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

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