Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application

Hsu, Ren-Fang; Hou, Yunfei; Yen, F.Y.; Chang, V.S.; Lim, Ra.; Hung, C.L.; Yao, L.G.; Jiang, Jun; Lin, Hsia Yu; Chiou, Jian-Yuan; Yin, K.M.; Lee, J.J.; Hwang, R.L.; Jin, Y.; Chang, Shu-Hao; Tao, Hun-Jan; Chen, S.C.; Liang, Mong–Song; Ma, T.P.

doi:10.1109/vlsit.2006.1705192

Cited by 15 publications

(3 citation statements)

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“…With the scaling of CMOS and VLSI devices to sub 100 nm MOSFET have significant use in the analog circuits such as in amplification, switching [1] and many more applications. MOSFET suffer from effects like Negative Bias Temperature Instability (NBTI), Short Channel Effects (SCE), Drain Induced Barrier Lowering (DIBL) and Hot Carrier Emissions.…”

Section: Introductionmentioning

confidence: 99%

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Gauba¹,

Pratap²,

Rewari³

et al. 2019

Semicond. Sci. Technol.

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In this paper, an analytical model has been developed to analyze the impact of trap charges on Dual Metal Gate-All-Around (DMGAA) MOSFET with BaTiO 3 -SrTiO 3 epitaxial oxide layer as gate stack using Greens function and conformal mapping. Trap charges have been induced to observe the changes in surface potential, electric field and drain current. To further investigate the impact of trap charges the trap density is varied. This enhances the drain current with high I ON /I OFF ratio. The analytical results so obtained are compared with the simulated data and are in good agreement thus validating the proposed model. It is also proposed that the device can offer high performance, low leakage power along with high gain and is perfect for analog RF applications. It can be concluded that proposed DMGAA MOSFET is a promising device and a suitable replacement for the existing conventional GAA MOSFETs.

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Section: Introductionmentioning

confidence: 99%

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Gauba¹,

Pratap²,

Rewari³

et al. 2019

Semicond. Sci. Technol.

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“…In addition, excluding V t control, forming two different highk/metal gate stacks, including the separating of high-k and metal gate of n/pMOS in different regions of the wafer and the synchronous etching of n/pMOS MIPS structure, is also a challenge. Some studies have already been performed on dual metal gate integration [14] and MIPS structure etching, [15] but to our knowledge, the separating of TaN/HfSiON (nMOS) and TaN/Mo/HfSiAlON (pMOS) MIPS structure and the dry etching of two different thickness and composition gate-stacks at the same time have not been explored before.…”

Section: Introductionmentioning

confidence: 99%

Key technologies for dual high- k and dual metal gate integration

Li¹,

Xu²,

Wang³

2018

Chinese Phys. B

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The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiO x . Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1 (NH 4 OH:H 2 O 2 :H 2 O = 1 : 1 : 5) and DHF-based solution for the selective removing of nMOS TaN and HfSiON and by BCl 3 -based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON. After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl 3 /SF 6 /O 2 /Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl 3 /Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

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“…The metal gate M1 is thus rightfully known as the Control Gate and the metal M2 as the Screen Gate. Fabrication techniques for DMG CMOS [20][21][22][23] structure are reported in literature. DMG CMOS device with gate length of 55nm is already fabricated [21].…”

Section: Introductionmentioning

confidence: 99%

An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

Bhushan¹,

Sarangi²,

Krishna³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application

Cited by 15 publications

References 1 publication

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Key technologies for dual high- k and dual metal gate integration

An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

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Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application

Cited by 15 publications

References 1 publication

Traps induced Greens function based mathematical modeling for BaTiO3–SrTiO3 gate stack dual metal GAA MOSFET

Traps induced Greens function based mathematical modeling for BaTiO3–SrTiO3 gate stack dual metal GAA MOSFET

Key technologies for dual high- k and dual metal gate integration

An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

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Product

Resources

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Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET