CMOS Scaling with III-V Channels for Improved Performance and Low Power

Hill, Richard J.; Oh, Jungwoo; Park, Chanro; Barnett, Joel; Price, J.E.; Huang, Jung-Tang; Goel, N.; Loh, Wann Jia; Kirsch, P. D.; Majhi, P.; Jammy, R.

doi:10.1149/1.3569926

Cited by 4 publications

(3 citation statements)

References 11 publications

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“…The high quality and thin III-V channel formation on Si substrates seems to be much more difficult than Ge, although the III-V channel growth on Si using thick III-V buffer layers and the MOSFET applications have been demonstrated [36][37][38]. Actually, formation techniques of thin III-V-OI structures are hardly known.…”

Section: Iii-v Mosfet Technologies 1 Iii-v Channel Formation On Simentioning

confidence: 99%

“…One is the direct growth of III-V materials on Si substrates, similar to Ge. Although efforts to reduce the buffer layer thickness in wafer level direct growth of III-V materials on Si substrates have been made [36][37][38], the buffer layer thickness is still 1 Pm order. Another promising approach is the micro selective growth of III-Vs on Si [40][41][42][43][44][45].…”

Section: Iii-v Mosfet Technologies 1 Iii-v Channel Formation On Simentioning

confidence: 99%

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Prospective and Critical Issues of III-V/Ge CMOS on Si Platform

Takagi

Takenaka

2011

ECS Trans.

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III-V/Ge CMOS on Si platform, realized by heterogeneous integration, is expected to provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. Among them, high speed/low power logic CMOS using III-V/Ge channels are promising device solution for further progress in scaled CMOS. While many critical issues have been well recognized for them, we present possible solutions to break through these difficulties in this paper. Main critical issues of Ge/III-V MOSFETs on Si platform are (1) formation of MIS gate stacks with superior interfacial properties and (2) formation of Ge/III-V channel layers on Si substrates. Ge MOS interfaces with thermally-oxidized GeO 2 are promising for the superior interface properties as well as the high inversion-layer mobility. SGOI/GOI structures based on Ge condensation are promising for future ultrathin SGOI/GOI MOSFETs. A wafer bonding technique can be potential solutions of III-V MOSFETs on Si platform. Using this technique, the operation of ultrathin body/ultrathin BOX InGaAs-OI MOSFETs are demonstrated. Also, surface nitridation and surface orientation engineering are shown to be effective in III-V MOS interface control. Finally, novel metal S/D InGaAs MOSFETs utilizing NiInGaAs alloys are proposed and demonstrated.

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Section: Iii-v Mosfet Technologies 1 Iii-v Channel Formation On Simentioning

confidence: 99%

Section: Iii-v Mosfet Technologies 1 Iii-v Channel Formation On Simentioning

confidence: 99%

Prospective and Critical Issues of III-V/Ge CMOS on Si Platform

Takagi

Takenaka

2011

ECS Trans.

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“…To make this a reality, substantial undertaking has gone into finding solutions for the technological challenges facing III-V MOSFETs (1,6). InGaAs, in particular, has been the centre of extensive research effort with remarkable progress being made in the in the critical areas of gate stack (7,8), parasitic resistance (9) and III-V/Si heterointegration (10). Recent impressive transistor performances (11)(12)(13) clearly demonstrate the extent to which III-V nMOSFET technology has matured.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options

Peralagu

Ignatova

et al. 2015

ECS Trans.

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Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

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