Comparative Study of SRT-Dividers in FPGA

Sutter, Gustavo; Bioul, Géry Jean Antoine; Deschamps, Jean-Pierre

doi:10.1007/978-3-540-30117-2_23

Cited by 17 publications

(17 citation statements)

References 3 publications

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“…An extensive comparative study of divider implementations on FPGAs, including all kinds of restoring, non-restoring, and SRT dividers has been presented in [1]. It is even possible to implement dividers based on the small embedded 18x18 multiplier blocks [3], [4].…”

Section: Implementation Analysismentioning

confidence: 99%

Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time

Beguenane

Mailloux

Simard

et al. 2006

2006 Canadian Conference on Electrical and Computer Engineering

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Abstract-The aim of this research is to implement sensorless vector control algorithms on a single, eventually reconfigurable, chip, with a computation timing constraint of, at most, 1-6 microseconds, and a concern for implementation cost. In this article, we discuss the implementation problems and tradeoffs involved in meeting these goals on Field-Programmable Gate Arrays (FPGAs). To be able to fit a complete induction motor vector controller on a single, inexpensive FPGA chip, we estimate the area/time requirements of each module involved in sensorless vector control. We discuss, in particular, the tradeoffs of implementing the key modules, the speed and flux observers and the Clarke and Park transformations. The speed and flux observers here under consideration are extended Kalman filter-based.

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Section: Implementation Analysismentioning

confidence: 99%

Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time

Beguenane

Mailloux

Simard

et al. 2006

2006 Canadian Conference on Electrical and Computer Engineering

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“…Its advantage lies in simple control logic, but the drawbacks are high computational delay, large area consumption, and the number of iteration cycles. The non-restoring algorithm [ 19 , 20 , 21 , 22 ] adds a certain control logic to the restoring algorithm. Only one subtraction or addition is performed per iteration, and no additional restoring operations are required.…”

Section: Introductionmentioning

confidence: 99%

“…However, its quotient selection logic is more complex. Most embedded processor floating-point units use the SRT algorithm [ 2 , 21 , 23 , 24 , 25 ]. The SRT algorithm has different iteration cycles depending on the radix.…”

Section: Introductionmentioning

confidence: 99%

A Low-Latency Divider Design for Embedded Processors

Wei

Yang

Chen

2022

Sensors

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Division is generally regarded as a low-frequency, high-latency operation in integer operations. Division is also the operation that stalls the processor pipeline most frequently. In order to improve the overall performance of embedded processors, a low-delay divider for embedded processors was designed. Based on the non-restoring algorithm, the divider uses a compound adder to execute addition and subtraction simultaneously and reduces the iteration path delay. By shifting the operands to align the most effective bits, the divider dynamically adjusts the number of iteration cycles to reduce the average number of cycles in the division process. The divider design was simulated by Modelsim and implemented on a FPGA board for verification. Synthesized in a Semiconductor Manufacturing International Corporation (SMIC) 65 nm Low Leakage process, the achieved frequency of the design was up to 500 MHz and the area cost was 5670.36 μm2. Compared with other dividers, the proposed divider design can reduce the delay of single iteration by up to 45.3%, save the average number of iteration cycles by 20–50%, and save the area by 23.3–86.1%. Compared with other dividers implemented on FPGA, it saves LUTs by 36.47–59.6% and FFs by 67–84.28%, runs 2–6.36 times faster. Therefore, the proposed design is suitable for embedded processors that require low power consumption, low resource consumption, and high performance.

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“…Digit-recurrence algorithm is based on iterative subtraction, including restoring [4], non-restoring [5], and Sweeney-Robertson-Tocher (radix-n SRT) algorithm (SRT is in fact one of non-restoring algorithms) [6]. It works digit by-digit with an iterative-type subtraction and produces a quotient in sequence [7].…”

Section: Introductionmentioning

confidence: 99%

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Xia

Liu

et al. 2021

Applied Sciences

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Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point division in actual microprocessors, this paper proposes a low-latency architecture with a multi-precision architecture for floating-point division which will meet the IEEE-754 standard. There are three parts in the floating-point division design: pre-configuration, mantissa division, and quotient normalization. In the part of mantissa division, based on the fast division algorithm, a Predict–Correct algorithm is employed which brings about more partial quotient bits per cycle without consuming too much circuit area. Detailed analysis is presented to support the guaranteed accuracy per cycle with no restriction to specific parameters. In the synthesis using TSMC, 90 nm standard cell library, the results show that the proposed architecture has ≈63.6% latency, ≈30.23% total time (latency × period), ≈31.8% total energy (power × latency × period), and ≈44.6% efficient average energy (power × latency × period/efficient length) overhead over the latest floating-point division structure. In terms of latency, the proposed division architecture is much faster than several classic processors.

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Comparative Study of SRT-Dividers in FPGA

Cited by 17 publications

References 3 publications

Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time

Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time

A Low-Latency Divider Design for Embedded Processors

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

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