Design Technique of an On-Chip, High-Voltage Charge Pump in SOI

Hoque, Mohammad Rashedul; Ahmad, Tausif; McNutt, Ty; Mantooth, Alan; Mojarradi, Mohammad

doi:10.1109/iscas.2005.1464542

Cited by 12 publications

(8 citation statements)

References 12 publications

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“…However, the drawbacks of this technology are still the limited drainto-source voltage compared to the HV nowadays applications, the lacking of HV capacitors, and potential back-gate turn-on. The HV produced by a charge pump using this technology still well below 100 V [16].…”

Section: Hv Integrated Circuits Using Fg Protectionsmentioning

confidence: 95%

High-voltage DMOS integrated circuits using floating-gate protection technique

Chebli

El‐Sankary

Savaria

2009

Analog Integr Circ Sig Process

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An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level shifting involves complex circuits that reduce the speed besides requiring of large power and area. In this paper, a simple and efficient protection technique for gate-oxide breakdown is achieved by connecting a capacitor divider structure to the floating-gate node of HV transistor to increase its effective gate oxide thickness. Several HV circuits, including: positive and negative HV doublers and level-up shifters suitable for ultrasound sensing systems are built successfully around the proposed technique. These circuits were implemented with 0.8 lm CMOS/DMOS HV DALSA process. Simulation and experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 200 V.

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Section: Hv Integrated Circuits Using Fg Protectionsmentioning

confidence: 95%

High-voltage DMOS integrated circuits using floating-gate protection technique

Chebli

El‐Sankary

Savaria

2009

Analog Integr Circ Sig Process

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“…One approach is to use devices that can be implemented on top of the field oxide as the field oxide has a high breakdown voltage [4], another approach is to use multiple ASICs [5]. It is also possible to use processes that are designed for HV applications such as Silicon On Insulator (SOI) processes which has been the approach in [6], [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology

Toft

Jørgensen

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.

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“…Besides, charge pump circuits can be also used in some low-voltage designs to improve the circuit performance [3]. In the MEMS applications, the charge pump circuit must provide the output voltage higher than 15 V, even to 60 V [4], [5]. Early, the pn-junction diodes were used in the charge pump circuit.…”

Section: Introductionmentioning

confidence: 99%

On-Chip High-Voltage Charge Pump Circuit in Standard CMOS Processes With Polysilicon Diodes

Ker

Chen

2005

2005 IEEE Asian Solid-State Circuits Conference

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An on-chip high-voltage charge pump circuit realized with the polysilicon diodes in standard (bulk) CMOS process is presented in this paper. Because the polysilicon diodes are fully isolated from the substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed charge pump circuit has been fabricated in a 0.25-µm 2.5-V standard CMOS process. The output voltage of the 12-stage charge pump circuit can be pumped up to 28.08 V, which is much higher than the n-well/psubstrate breakdown voltage (18.9 V) in a 0.25-µm 2.5-V standard CMOS process. I.

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Design Technique of an On-Chip, High-Voltage Charge Pump in SOI

Cited by 12 publications

References 12 publications

High-voltage DMOS integrated circuits using floating-gate protection technique

High-voltage DMOS integrated circuits using floating-gate protection technique

Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology

On-Chip High-Voltage Charge Pump Circuit in Standard CMOS Processes With Polysilicon Diodes

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