Drivers for 3D Integration

Garrou, Philip E.; Vitkavage, S.C.; Arkalgud, Sitaram

doi:10.1002/9783527623051.ch2

Cited by 11 publications

(6 citation statements)

References 5 publications

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“…3D integration is an emerging technology to overcome RC delay for submicron technology and to allow heterogeneous integration of chips, also known as the 'System-in-Package' concept [1]. These 3D stacked chips make use of vertical interconnects, i.e.…”

Section: Introductionmentioning

confidence: 99%

Continuous deep reactive ion etching of tapered via holes for three-dimensional integration

Lamy

Roozeboom

et al. 2008

J. Micromech. Microeng.

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A continuous SF 6 /O 2 plasma process at room temperature has been used to etch tapered through-silicon vias using a DRIE-ICP tool. These features (10-100 μm in diameter) are aimed for applications in 3D integration and MEMS packaging. The effects of various process parameters such as O 2 flow rate, platen bias, pressure and substrate temperature on the via profile (depth, slope angle and aspect ratio) development are investigated. The etching mechanism was also studied and x-ray photoelectron spectroscopy (XPS) analysis reveals a SiO x passivation layer of the order of ∼2 nm on the via sidewall and a substantial temperature dependence. Both tapering and anisotropy of etching depend on this passivation layer formation. Finally, suitable tapered vias with an aspect ratio of ∼5 and a slope angle of ∼83• are obtained by properly balancing the etching regimes. In this condition, a maximum etch rate of 7 μm min −1 is achieved.

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Section: Introductionmentioning

confidence: 99%

Continuous deep reactive ion etching of tapered via holes for three-dimensional integration

Lamy

Roozeboom

et al. 2008

J. Micromech. Microeng.

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“…First, a DRIE Bosch process was used to etch a periodic array of HAR TSVs [36] of 5 µm diameter by 50 µm depths on both wafers. Then, prior to any metallization process, both wafers were prepared using the so-called RCA clean [2]. First, a Standard Clean 1 (SC-1) (a mixture of H2O2, NH4OH and H2O) was performed to remove organic residues and particles from the Si substrate.…”

Section: A Tsvs Samples Fabricationmentioning

confidence: 99%

“…In 3D integration, dies are stacked and connected to each other using vertical interconnections, insulated from the silicon (Si) substrate, called through silicon vias (TSV). This technology allows better electrical performances, higher transistor density and advanced functionalities [1], [2].…”

Section: Introductionmentioning

confidence: 99%

Wet Metallization of High Aspect Ratio TSV Using Electrografted Polymer Insulator to Suppress Residual Stress in Silicon

Dequivre

Kolhatkar

Youssef

et al. 2017

IEEE Trans. Device Mater. Relib.

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Through-Silicon-Vias (TSV) are the key to 3D integrated microsystems. Their fabrication leads to reliability issues linked to the thermo-mechanical stress induced in the silicon around the vias. In this work, we propose to reduce the silicon residual stress in high aspect ratio copper TSVs (HAR TSV) using an electrografted polymer insulator, poly-4-vinylpyridine (P4VP), in replacement of the traditional silicon oxide layer. We use Raman spectroscopy to make the first investigation of the residual stress in the Si around P4VP insulated TSVs and compare it to SiO2 insulated TSVs. The results show that P4VP acts as a stress buffer layer because of its particular mechanical properties as the measured residual stress in Si is significantly reduced at room temperature around the polymer insulated HAR TSVs. The potential benefits of such a technology are not only a better thermo-mechanical reliability of 3D integrated microsystem, but also a greater integration density.

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“…In general the TSV concept includes the routing from one side of the device trough itself to its backside. In order to yield functional TSVs a precise front to backside alignment process is needed in any case regardless which TSV approach has been chosen [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Front to backside alignment for TSV based 3D integration

Windrich

Schenke

2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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The demand of smaller form factors, multifunctional microelectronics and thereby the need for improved electrical performance and reliability is the key driver for the development of 3D technologies with through silicon vias (TSV). Different through silicon via approaches are available and have pros and cons regarding process integration. But in any case a front to backside alignment is necessary regardless if a via first, via middle or via last approach has been chosen. This paper discusses available alignment technologies and strategies which are needed for front to backside alignment on 3D TSV integration examples. Alignment results with a 300mm mask aligner for a 2.5D interposer application and a via last approach are shown. The top side overlay accuracy between filled through silicon vias and the next photoresist layer showed a variation of 3 sigma = 1.7 mu m. The overlay accuracy for the wafer backside between TSV and the first backside photoresist layer was doubled to 3 sigma = 3.4 mu m. The difference was caused by the used alignment method. Furthermore the influence of wafer deformation (warpage / bow) on backside alignment accuracy is discussed for an interposer application

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Drivers for 3D Integration

Cited by 11 publications

References 5 publications

Continuous deep reactive ion etching of tapered via holes for three-dimensional integration

Continuous deep reactive ion etching of tapered via holes for three-dimensional integration

Wet Metallization of High Aspect Ratio TSV Using Electrografted Polymer Insulator to Suppress Residual Stress in Silicon

Front to backside alignment for TSV based 3D integration

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