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Three-dimensional (3D) die stacking using through silicon viae (TSV) promises significant improvements in performance, power consumption and size over traditional edgeconnected die stacking (e.g. wire bonds) or package -on-package (PoP) based approaches. 3D integrat ed circuits (3D -IC) using TSV will enable new system in package (SiP) applications, especially where ultra -high memory bandwidth at moderate power consumption is needed. This paper describes the technology elements for a succ essful implementation of TSV in high volume manufacturing (HVM) with special focus on the socalled "TSV mid" integration flow being developed at SEMATECH. The maturity and readiness of each process module for HVM is assessed.In addition to technological feasibility and manufacturing readiness, 3D-IC adoption requires an environment of agreed upon specifications, standards, and tools (3D ecosystem). Progress toward a well defined 3D ecosystem by SEMATECH and many other organizations is described in part III of this paper.

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