Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging

Topper, Michael J.; Auersperg, J.; Glaw, V.; Kaskoun, K.; Prack, Edward R.; Keser, Beth; Coskina, P.; Jäger, D.; Fetter, D.; Ehrmann, O.; Samulewicz, K.; Meinherz, C.; Fehlberg, S.; Karduck, C.; Reichl, H.

doi:10.1109/ectc.2000.853121

Cited by 37 publications

(8 citation statements)

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“…[21LJ and G = G1 + G11 Figure 1 : Schematic of the near tip nodes for the VCCT, where b is the uniform crack width, are the nodal forces at node i in direction U, are the relative displacements between the nodes i and j in direction u. zM denotes the distance between the nodes 1 and 3(4) as well as between 2 and 5 (6) Assuming that the results of all such failure investigations are consistent the valuing parameters give a basis for a ranking of electronics assemblies from reliability stand point. Moreover, it provides the chance for parameter studies, sensitivity analyses or design optimizations.…”

Section: Thermo-mechanical Reliability Assessmentmentioning

confidence: 99%

<title>Parameterized FE-modeling and interfacial fracture toughness investigations towards reliability enhancements of advanced plastic packages</title>

Auersperg

Dudek

Michel

2002

Design, Test, Integration, and Packaging of MEMS/MOEMS 2002

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Damage, fatigue and failure of advanced electronic packages of MEMS and related systems are often caused by their growing use under harsh environmental conditions as well as extreme temperatures. Consequently, their thermomechanical reliability becomes more and more one of the most important preconditions for adopting it in industrial applications. Various kinds of inhomogeneity, residual stresses from several steps of the manufacturing process along with the fact that microelectronic packages are basically compounds of materials with quite different Young's moduli and thermal expansion coefficients contribute to interface delamination, chip cracking and fatigue of solder interconnects. Subsequently, numerical investigations by means of nonlinear FEA, fracture mechanics concepts are frequently used for design optimizations using sensitivity analyses. Parameters used for such sensitivity analyses are typically materials parameters, geometrical and physical boundary conditions but. Especially, the influence of geometrical design parameters on the thermo-mechanical reliability is more and more asked for.This paper intends to demonstrate and discuss advantages and needs of using fully parameterized finite element modeling techniques for design optimizations on the basis of damage evaluation and fracture mechanics approaches.For improving that method, the evaluation of mixed mode interface delamination phenomena' and thermal fatigue of solder joints 2,3 were combined with experimental investigations using a gray scale correlation method. Some results of examinations with respect to different meshing techniques and rules should help to clarify their influence on FEA results.So, the combination of numerical and experimental investigations should give a reliable basis for understanding and evaluating failure mechanisms for arising the thermo-mechanical reliability of microcomponents.

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Section: Thermo-mechanical Reliability Assessmentmentioning

confidence: 99%

<title>Parameterized FE-modeling and interfacial fracture toughness investigations towards reliability enhancements of advanced plastic packages</title>

Auersperg

Dudek

Michel

2002

Design, Test, Integration, and Packaging of MEMS/MOEMS 2002

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“…Using i.e. BCBTi:W/Cu -BCB redistribution, BCB is acting as first (Pass 1) and second passivation (Pass 2) embedding the redistribution leads made out of Ti:W/Cu [4]. A ball grid array of lead-free solder may be applied using a Ni/Au under-bump-metallization.…”

Section: Wafer-level-packaging Using Si-via-contactsmentioning

confidence: 99%

“…Most of the successful wafer-level-packaging technologies introduced in the past [3,4] are using polymers as dielectric material for the passivation of microelectronic elements as well as electrical insulation of the device and the redistribution leads of the package. A broad class of materials have been developed ranging from epoxy-based materials and spin-on polymers to polyimids and BCB.…”

Section: Wafer-level-packaging and Redistribution Using Polymermentioning

confidence: 99%

Novel Hermetic Wafer-Level-Packaging Technology using Low-Temperature Passivation

Leib

Mund

Topper

2005

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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In the past decade wafer level packaging (WLP) has been proven to be a very competitive solution regarding performance, miniaturization and costs for a wide range of applications. However, they are up to now not matching the performance of hermetically sealed Glass or Glass-to-MetalSeal packages, esp. when considering application in extreme environment. In this paper a novel packaging technology is proposed, allowing hermetic passivation and encapsulation of microelectronic devices on wafer-level. This technology combines the unique properties of microstructuring of glass on silicon process [1] with the capabilities of a wafer-level packaging technology using Silicon-Via-Contacts [2]. This new processing technology is enabling hermetic encapsulation of devices on wafer-level comprising an unique, cost effective passivation process performed at temperatures below 120°C. Wafer-Level-Packaging and Redistribution using PolymerMost of the successful wafer-level-packaging technologies introduced in the past [3,4] are using polymers as dielectric material for the passivation of microelectronic elements as well as electrical insulation of the device and the redistribution leads of the package. A broad class of materials have been developed ranging from epoxy-based materials and spin-on polymers to polyimids and BCB.Acceptable microstructuring results can be achieved with those materials by plasma etching using a photo-resist mask or by choosing a class of intrinsic photosensitive passivation polymers applying lithography directly.Generally the polymer passivation has to be cured after application to the wafer. The degree of cure of that passivation materials has a strong impact on their passivation properties and therefore on the overall reliability of the packaged electronic devices. If thermal curing is applied, Tg of the polymers is systematically lower than the bake temperature. Standard curing conditions are in the range of 160°C to 380°C for several minutes to hours depending on the polymer material. Sensitive electronic devices i.e. CMOS or analog IC's may suffer significant loss of device performance when exposed to those curing conditions.

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“…Fraunhofer IZM has done initial studies on this doublebump structure [6]. After stencil printing the first level of bumps on the wafer, Fraunhofer dispensed different commerciallyavailable materials at each discrete device on the wafer to encapsulate the bumps, and chemical-mechanical polishing was used to open vias to the embedded bumps.…”

Section: Introductionmentioning

confidence: 99%

Encapsulated double-bump WL-CSP: design and reliability

Keser

Yeung²,

White³

et al.

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

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A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 x 8 array of bumps on a 5 x 5 mm 2 die. Micro Moiré Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported. IntroductionWafer-Level packaging is becoming a very popular method of packaging low to mid-I/O devices for several reasons: cost, size, and ease of testing. Cost is the largest force driving wafer-level packaging.Using batch processing, an entire wafer can be packaged instead of packaging each singulated die. Wafer level packaging reduces packaging steps, eliminates the use of underfill, and allows for centralized processing in the fab. Also, packaging the wafer allows for a high degree of process integration due to the use of fab-type processing such as thin films and lithography which decreases cost. Centralized packaging in the fab also reduces packaging time and inventory, since devices no longer have to be packaged separately between the fab and the assembly houses. Size is also a driving force for wafer-level packaging. The footprint of a WL-CSP is the same as the die. Wafer-level burn-in and test (WLBT) is also driving the industry toward WL-CSP solutions. Test will no longer be necessary before packaging. A completely packaged wafer can be burned-in and tested after the final packaging step resulting in known good packages (KGP). Testing at the wafer level can reduce test costs by as much as 50%, requires less test capital, and reduces the number of test steps.

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Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging

Cited by 37 publications

References 4 publications

<title>Parameterized FE-modeling and interfacial fracture toughness investigations towards reliability enhancements of advanced plastic packages</title>

<title>Parameterized FE-modeling and interfacial fracture toughness investigations towards reliability enhancements of advanced plastic packages</title>

Novel Hermetic Wafer-Level-Packaging Technology using Low-Temperature Passivation

Encapsulated double-bump WL-CSP: design and reliability

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