Fabrication of wafer scale, aligned sub-25nm nanowire and nanowire templates using planar edge defined alternate layer process

Sonkusale, Sachin R.; Amsinck, Christian; Nackashi, David P.; Spigna, Neil H. Di; Barlage, Douglas W.; Johnson, Mark A.; Franzon, Paul D.

doi:10.1016/j.physe.2005.01.010

Cited by 21 publications

(11 citation statements)

References 18 publications

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“…Either approaches have been used in order to define dense NW molds. The pattern of such nanomolds is subsequently transferred onto a different substrate by nanomold imprint lithography in order to define layers of micrometer long and parallel NWs [21], [23].…”

Section: A Spacer Technologymentioning

confidence: 99%

“…Unlike previous approaches that used the MSPT to define simple layers of parallel NWs [4], [13], [20], and those that used the MSPT to define nanomolds to pattern NWs [19], [21], [23], this paper demonstrates for the first time 1) that not only layers of parallel NWs, but also dense NW crossbars can be fabricated with the MSPT, and 2) that MSPT-based crossbars can be obtained in a self-aligned and maskless process without the utilization of any nanomold. The scalability of the as-fabricated poly-Si crossbars is studied, and the characterization of the access devices operating as polySiNW FETs is performed for the first time.…”

Section: Spacer-based Nw Crossbarsmentioning

confidence: 99%

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Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Jamaa

Cerofolini

Micheli

et al. 2011

IEEE Trans. Nanotechnology

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Abstract-In this paper, we demonstrate the ability of the multispacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution andCMOS processing steps. We characterize single spacers operating as poly-Si nanowire field effect transistors . We demonstrate also the possibility to lay a spacer perpendicularly to a set of parallel spacers in a crossbar fashion. The extrapolated cross-point density from the small 4 × 1-array is in the range of 10 10 cm −2 . We discuss the applications of this technique to improve the density of previously reported poly-SiNW memories and as a future framework for nanowire crossbars and decoders. Then we analyze the limitations and costs of the proposed technique.

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Section: A Spacer Technologymentioning

confidence: 99%

Section: Spacer-based Nw Crossbarsmentioning

confidence: 99%

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Jamaa

Cerofolini

Micheli

et al. 2011

IEEE Trans. Nanotechnology

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“…STL is based on the transformation of thin layers deposited on mesas into nanoscale ribs [11][12][13][14][15][16][17], slots [18][19][20][21] and vertically stacked multilayers [22][23][24]. It was originally developed for CMOS applications [25], and processes for FinFET fabrication have received increasing attention in recent years with the drive towards strongly submicron channels [26][27][28][29][30][31][32].…”

Section: Introductionmentioning

confidence: 99%

NEMS by Sidewall Transfer Lithography

Liu

Syms

2014

J. Microelectromech. Syst.

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-A batch fabrication process for nano-electromechanical systems (NEMS) based on sidewall transfer lithography (STL) is demonstrated. STL is used to form nanoscale flexible silicon suspensions entirely by conventional photolithography. A two-step process for combining microscale and nanoscale features is used to fabricate double-ended and single-ended electrothermal actuators with a minimum feature width of 100 nm and an aspect ratio of 40 : 1. All devices are fabricated by deep reactive ion etching in 4.5 µm thick silicon using bonded silicon-on-insulator material. The process could allow low cost fabrication of nanoscale sensors and actuators.

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“…The multi-spacer patterns can also be created by a so-called planar edge defined alternate layer (PEDAL) process [8,9]. The PEDAL process consists of: (1) fabrication of trench-like structures with vertical sidewalls; (2) alternating deposition of materials upon the trench-like structure, e.g.…”

Section: Introductionmentioning

confidence: 99%

Multi-silicon ridge nanofabrication by repeated edge lithography

Zhao¹,

Berenschot²,

Jansen³

et al. 2009

Nanotechnology

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We present a multi-Si nanoridge fabrication scheme and its application in nanoimprint lithography (NIL). Triple Si nanoridges approximately 120 nm high and 40 nm wide separated by 40 nm spacing are fabricated and successfully applied as a stamp in nanoimprint lithography. The fabrication scheme, using a full-wet etching procedure in combination with repeated edge lithography, consists of hot H 3 PO 4 acid SiN x retraction etching, 20% KOH Si etching, 50% HF SiN x retraction etching and LOCal Oxidation of Silicon (LOCOS). Si nanoridges with smooth vertical sidewalls are fabricated by using Si 110 substrates and KOH etching. The presented technology utilizes a conventional photolithography technique, and the fabrication of multi-Si nanoridges on a full wafer scale has been demonstrated.

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Fabrication of wafer scale, aligned sub-25nm nanowire and nanowire templates using planar edge defined alternate layer process

Cited by 21 publications

References 18 publications

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

NEMS by Sidewall Transfer Lithography

Multi-silicon ridge nanofabrication by repeated edge lithography

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