Fast split background calibration for pipelined ADCs enabled by slope mismatch averaging technique

Adel, Hussein; Louërat, Marie-Minerve; Sabut, Marc

doi:10.1049/el.2012.0357

Cited by 16 publications

(4 citation statements)

References 5 publications

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“…Hence, the overall gain of ADC A needs to be scaled by a term alpha [14] in order to make the two output transfer curves parallel to each other. The alpha can be calculated from the ratio of the slopes of the two fine ADC outputs [18].…”

Section: Mismatch Between Split-adcsmentioning

confidence: 99%

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration

Sehgal¹,

Goes²,

Bult³

2015

IEEE J. Solid-State Circuits

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A 12 bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered to achieve higher energy efficiency and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical op amp implementation, the settling accuracy of the residue amplifier was relaxed by a factor of more than 3x in the first two stages and by 2x in the remaining stages. The ADC was implemented in 40 nm digital CMOS and shows a Schreier figure-ofmerit of 157.5 dB at 1 V supply, sampling at 195 MS/s, with an SNDR/SFDR of 64.8 dB/82 dB. While working in continuous background mode, the split-ADC calibration improved the ADC SFDR by 37 dB within 70,000 samples.Index Terms-Analog-to-digital conversion, background calibration, class-A amplifier, nonlinearity calibration, pipelined ADC, settling accuracy, split-ADC, switched-capacitor circuits.

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Section: Mismatch Between Split-adcsmentioning

confidence: 99%

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration

Sehgal¹,

Goes²,

Bult³

2015

IEEE J. Solid-State Circuits

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“…Using the raw bits of the 1st split stages, two calibration outputs are detected in the background for each segment of the calibrated stage residue of ADC channel , along with the corresponding outputs of ADC channel as illustrated in the figure . The slopes of the residue segments of both split ADC channels, and , are then calculated and the gain error mismatch correction parameter for all segments of the residue is given by the average [8]:…”

Section: A Slope Mismatch Averagingmentioning

confidence: 99%

“…An interesting split ADC technique is presented in [7], which performs a rapid calibration of MDAC errors. This technique is further developed in [8], which gives more accurate and faster calibration using slope mismatch averaging (SMA) to correct for amplifier finite gain and sampling capacitor mismatch. This work aims at extending the SMA technique in split ADC for multistage calibration, and considering its practical limits by analysis, simulations and applying it on a 40 nm pipeline A D C .S e c t i o nI Ip r e s e n t sa no v e r v i e wo nt h es p l i tA D Cc a l ibration.…”

Section: Introductionmentioning

confidence: 99%

Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs

Adel

Sabut

Louërat

2015

IEEE Trans. Circuits Syst. I

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A fully deterministic digital background calibration for pipeline ADCs is presented. The proposed approach is based on split ADC concept to give the shortest background calibration time with high accuracy. A slope mismatch averaging technique is employed in a multistage calibration scheme to deterministically detect the circuit errors without any iterative operations or feedback loops, which render it fast and accurate. Analysis and behavioral simulations for the developed multistage calibration demonstrate the efficiency of this technique and its merit over the LMS-based techniques. Practical considerations have been considered and the proposed calibration has been applied on a 200 MS/s 40 nm CMOS split pipeline ADC to correct for the capacitor mismatch and the amplifier finite gain. The post-layout simulation results show a very fast calibration cycle, where the ADC achieves more than 11 ENOB in less than 1600 clock cycles.

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“…This type of mismatch is not included in the following calibration system, since we assume that the harmonic distortion mismatch is neglected. The harmonic distortion issue is assumed to be calibrated at the low-speed ADC level [8].…”

Section: Harmonic Distortion Mismatchmentioning

confidence: 99%