Highly scalable ballistic injection AND-type (BiAND) flash memory

Wu, Meng-Yi; Dai, Sheng-Huei; Hu, Shu‐Fen; Yang, En-Yu; Hsu, Charles Ching–Hsiang; King, Ya‐Chin

doi:10.1109/ted.2005.860636

Cited by 6 publications

(1 citation statement)

References 13 publications

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“…Source-side injection [2] programming is the most promising scheme for increasing injection efficiency without any constraints on the optimization of gate and drain voltages. Recent advancements have successfully demonstrated the low-voltage operations in embedded applications [3][4][5][6]. Asymmetrical split-gate cells are typically adopted to decouple the channel hot electrons from the lateral drain field, while the complex addressing circuitry, enlarged cell size and extra process steps limit the use of such asymmetrical split-gate cells in practical flash technology.…”

Section: Introductionmentioning

confidence: 99%

Source-side injection Schottky barrier flash memory cells

Shih

Yeh

Liang

et al. 2009

Semicond. Sci. Technol.

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This work presents a novel Schottky barrier flash cell with promising source-side injection programming. The effects of the Schottky barrier on source-side injection programming are demonstrated by two-dimensional device simulations. The unique Schottky barrier at the source/channel interface significantly promotes the amount of source-side hot electrons to provide high injection efficiency at considerably low voltages without compromising between gate and drain biases. The new source-side injection Schottky barrier flash cell, which has a compact floating-gate structure with a metallic source/drain, is proposed for the first time as future flash memory.

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Section: Introductionmentioning

confidence: 99%

Source-side injection Schottky barrier flash memory cells

Shih

Yeh

Liang

et al. 2009

Semicond. Sci. Technol.

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Scaling considerations for sub-90 nm split-gate flash memory cells

Saha¹

2008

IET Circuits Devices Syst.

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A novel symmetrical split-gate structure for 2-bit per cell flash memory

Fang¹,

Kong²,

Gu³

et al. 2014

J. Semicond.

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A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection (SSI) and a poly-to-poly tunneling mechanism respectively.

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Highly scalable ballistic injection AND-type (BiAND) flash memory

Cited by 6 publications

References 13 publications

Source-side injection Schottky barrier flash memory cells

Source-side injection Schottky barrier flash memory cells

Scaling considerations for sub-90 nm split-gate flash memory cells

A novel symmetrical split-gate structure for 2-bit per cell flash memory

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