Influence of Si Surface Roughness on Electrical Characteristics of MOSFET with HfON Gate Insulator Formed by ECR Plasma Sputtering

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

“…The reliability of HfON thin films was also significantly improved by the reduction of Si surface roughness. In this section, the influence of Si surface roughness on the MOSFET characteristics is described [37,38,39]. The nMOSFETs with HfON gate insulator were fabricated on p-Si(100) substrates by typical gate-last process as follows [38,39].…”

“…In this section, the influence of Si surface roughness on the MOSFET characteristics is described [37,38,39]. The nMOSFETs with HfON gate insulator were fabricated on p-Si(100) substrates by typical gate-last process as follows [38,39]. After the isolation of active region by local oxidation of Si (LOCOS) process, the channel stopper was formed below field oxide (BF 3 , 100 keV, 1 Â 10 14 cm !2 ).…”

Variability Improvement by Si Surface Flattening of Electrical Characteristics in MOSFETs With High-k HfON Gate Insulator

“…Fig. 4 shows a comparison of ID-VD characteristics of fabricated MOSFETs [24,25]. The current drivability was remarkably increased from 12 μA/μm for the device w/o annealed to 18 μA/μm for the device with Ar/4.9%H2 annealed at VG-VTH=VD=1.5 V. This result was attributed to not only the decrease of EOT but improve of interface properties between Si and HfON by the Si surface flattening [24,26].…”

“…The annealing was carried out at 700-1000 o C for 60 min, and minimum surface roughness was obtained when the annealing temperature was 1000 o C [24]. Furthermore, it was found that the device characteristics of MOSFETs with high-k HfON gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering were significantly improved with decreasing the surface roughness [24][25][26][27]. In this paper, we have investigated the variability improvement of MOSFET characteristics with high-k HfON gate insulator by Si surface flattening utilizing Ar/4.9% ambient annealing at 1000 o C for 60 min.…”

“…Fig. 1 shows the typical gate-last n-channel MOSFET fabrication process used in this research [24,25]. After the active region isolation by local oxidation of Si (LOCOS), channel stop ion implantation was carried out at 100 keV with dose of 1x10 14 cm -2 for BF3 to form the heavily doped p + region underneath the field oxide.…”