InGaAs tri-gate MOSFETs with record on-current

Abstract

Abstract-We demonstrate InGaAs tri-gate MOSFETs with an on-current of I ON = 650 µA/µm at V DD = 0.5 V and I OFF = 100 nA/µm, enabled by an inverse subthreshold slope of SS = 66 mV/decade and transconductance of g m = 3 mS/µm, a Qfactor of 45. This is the highest reported I ON for both Si-based and III-V MOSFETs. These results continue to push III-V MOSFET experimental performance towards its theoretical limit. We find an improvement in SS from 81 to 75 mV/dec. as the effective oxide thickness (EOT) is scaled down from 1.4 to 1 nm, as well as improvements in SS, g d and DIBL from reducing the nanowire width. We also find that electron mobility remains constant as the width is scaled to 18 nm.

Low-frequency noise in nanowire and planar III-V MOSFETs

“…Common suggestions include gate-all-around architectures and novel materials at the device level [1][2][3][4], and monolithic 3D integration at the system level [4,5]. III-V nanowire (NW) MOSFETs, especially in a vertical architecture, can facilitate all these approaches at once and they have already demonstrated competitive or even superior performance in comparison with planar MOSFETs or FinFETs both in simulation [6] and in experiment [7][8][9][10].…”

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

“…III-V materials [6], [7] are attractive in such systems, both as CMOS and RF performance boosters [8], [9] through high electron mobility, as well as enablers of new functionalities, e.g., as direct band gap materials. Hybrid solutions, combining Si CMOS and III-V channels [10], [11], furthermore, can leverage the low thermal budget process of III-V FETs [12], typically sub-600 • C, to avoid degradation of reliability and performance of the bottom level Si CMOS. We have previously demonstrated III-V InGaAs MOSFETs directly integrated on top of a pre-processed Si CMOS wafer [13]- [16], with InGaAs MOSFET performance approaching but not yet matching state-of-the-art InGaAs devices fabricated on silicon substrate [17]- [21], a challenging target due to the difference in fabrication complexity.…”

Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

“…The aggressive downscaling of CMOS transistors demands for design solutions to obtain large drive currents at small supply voltage and preserve low leakage currents. The possible options for technology improvement include the reduction of source/drain series resistance that is responsible for a degradation of the transistor on-current by 30%-40%, 1,2 the use of semiconductors alternative to silicon, [2][3][4][5][6][7][8] the introduction of stressors, 9,10 and the development of device architectures beyond planar FETs such as multi-gate FETs (MuGFETs). 7,9,11 In particular, for CMOS generations beyond the 7-nm node, gate-all-around (GAA) nanowire FETs appear to be the most promising architecture.…”

“…The possible options for technology improvement include the reduction of source/drain series resistance that is responsible for a degradation of the transistor on-current by 30%-40%, 1,2 the use of semiconductors alternative to silicon, [2][3][4][5][6][7][8] the introduction of stressors, 9,10 and the development of device architectures beyond planar FETs such as multi-gate FETs (MuGFETs). 7,9,11 In particular, for CMOS generations beyond the 7-nm node, gate-all-around (GAA) nanowire FETs appear to be the most promising architecture. 1,2,5,[12][13][14][15] However, nanowire transistors still face significant challenges and, due to the high surface-tovolume ratio, the performance of these devices is strongly influenced by surface roughness (SR) and interface defects.…”