Instruction Offloading with HMC 2.0 Standard

Nai, Lifeng; Kim, Hyesoon

doi:10.1145/2818950.2818982

Cited by 30 publications

(22 citation statements)

References 6 publications

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“…3D die-stacked memory typically employs several DRAM dies on top of a logic die. For example, one type of diestacked memory, Hybrid Memory Cube (HMC) [29], [30], offers 8GB capacity per memory stack with link speeds up to 30Gbps (versus 1.6Gbps supported by DDR4) and peak ag- gregate bandwidth of 320GB/s/link. Recent studies show that die-stacked memory capacity is likely to scale to 16GB [16].…”

Section: Memory Networkmentioning

confidence: 99%

String Figure: A Scalable and Elastic Memory Network Architecture

Ogleari¹,

Qian

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Demand for server memory capacity and performance is rapidly increasing due to expanding working set sizes of modern applications, such as big data analytics, inmemory computing, deep learning, and server virtualization. One promising techniques to tackle this requirements is memory networking, whereby a server memory system consists of multiple 3D die-stacked memory nodes interconnected by a high-speed network. However, current memory network designs face substantial scalability and flexibility challenges. This includes (1) maintaining high throughput and low latency in large-scale memory networks at low hardware cost, (2) efficiently interconnecting an arbitrary number of memory nodes, and (3) supporting flexible memory network scale expansion and reduction without major modification of the memory network design or physical implementation. To address the challenges, we propose String Figure 1 , a highthroughput, elastic, and scalable memory network architecture. String Figure consists of (1) an algorithm to generate random topologies that achieve high network throughput and nearoptimal path lengths in large-scale memory networks, (2) a hybrid routing protocol that employs a mix of computation and look up tables to reduce the overhead of both in routing, (3) a set of network reconfiguration mechanisms that allow both static and dynamic network expansion and reduction. Our experiments using RTL simulation demonstrate that String Figure can interconnect over one thousand memory nodes with a shortest path length within five hops across various traffic patterns and real workloads.

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Section: Memory Networkmentioning

confidence: 99%

String Figure: A Scalable and Elastic Memory Network Architecture

Ogleari¹,

Qian

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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“…Graph traversals are bounded by irregular memory access patterns of graph property and a study [25] proposes to offload the graph property to hybrid memory cube [1] (HMC) by utilizing the atomic requests described in HMC 2.0 specification (that is limited to only integer operations and one memory operand).…”

Section: Applications Of Pimmentioning

confidence: 99%

“…The umbrella of NDP covers 2D-integrated Processing-In-Memory, 3D-stacked Processing-In-Memory (PIM) and In-Storage Processing (ISP). Existing studies show efficacy of processingin-memory (PIM) approach for simple map-reduce applications [16,28], graph analytics [6,25], machine learning applications [11,20] and SQL queries [24,34]. Researchers also show the potential of processing in non-volatile memories for I/O bound big data applications [12,30,33].…”

Section: Introductionmentioning

confidence: 99%

Identifying the potential of near data processing for apache spark

Awan

Ohara

Ayguadé

et al. 2017

Proceedings of the International Symposium on Memory Systems

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While cluster computing frameworks are continuously evolving to provide real-time data analysis capabilities, Apache Spark has managed to be at the forefront of big data analytics for being a unified framework for both, batch and stream data processing. There is also a renewed interest in Near Data Processing (NDP) due to technological advancement in the last decade. However, it is not known if NDP architectures can improve the performance of big data processing frameworks such as Apache Spark. In this paper, we build the case of NDP architecture comprising programmable logic based hybrid 2D integrated processing-in-memory and instorage processing for Apache Spark, by extensive profiling of Apache Spark based workloads on Ivy Bridge Server.

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“…Previous work shows that neither type of PIMs is an obvious performance winner, given the variety of applications that are likely to benefit from PIMs [19,1,2,32,51,33,65,20,4,13,65,33]. Therefore, we also examine the feasibility of a heterogeneous PIM design, which integrates both fixed-function and programmable PIM in the logic layer.…”

Section: Memory Stack Configurationsmentioning

confidence: 99%

“…The logic die offers sufficient silicon area and performance capability to implement various logic and computation functions, such as adders, memory copiers, CPU cores, and GPUs [13,4]. Recent studies [19,1,2,32,51,33,65,20,4,13,65,33] demonstrate that such integration technologies is likely to enable PIM in a practical manner.…”

Section: Introductionmentioning

confidence: 99%

Integrated Thermal Analysis for Processing In Die-Stacking Memory

Zhu

Wang

Liu

et al. 2016

Proceedings of the Second International Symposium on Memory Systems

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Recent application and technology trends bring a renaissance of the processing-in-memory (PIM), which was envisioned decades ago. In particular, die-stacking and silicon interposer technologies enable the integration of memory, PIMs, and the host CPU in a single chip. Yet the integration substantially increases system power density. This can impose substantial thermal challenges to the feasibility of such systems. In this paper, we comprehensively study the thermal feasibility of integrated systems consisting of the host CPU, die-stacking DRAMs, and various types of PIMs. Compared with most previous thermal studies that only focus on the memory stack, we investigate the thermal distribution of the whole processor-memory system. Furthermore, we examine the feasibility of various cooling solutions and feasible scale of various PIM designs under given thermal and area constraints. Finally, we demonstrate system run-time thermal feasibility by executing two high-performance computing applications with PIM-based systems. Based on our experimental studies, we reveal a set of thermal implications for PIM-based system design and configuration.

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Instruction Offloading with HMC 2.0 Standard

Cited by 30 publications

References 6 publications

String Figure: A Scalable and Elastic Memory Network Architecture

String Figure: A Scalable and Elastic Memory Network Architecture

Identifying the potential of near data processing for apache spark

Integrated Thermal Analysis for Processing In Die-Stacking Memory

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