Investigation of transient current characteristics with scaling-down poly-Si body thickness and grain size of 3D NAND flash memory

Lee, Sang-Ho; Kwon, Dae Woong; Kim, Seung Hyun; Baek, Myung-Hyun; Lee, Sungbok; Kang, Jung Sook; Jang, Woojae; Park, Byung‐Gook

doi:10.1016/j.sse.2018.11.009

Cited by 9 publications

(2 citation statements)

References 16 publications

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“…In the last decade, three-dimensional (3D) NAND flash charge trapping silicon-oxide-nitride-oxide-silicon (SONOS) memory has emerged as one of the most promising alternatives to floating gate non-volatile memory [1], [2]. Due to the increasing demand on non-volatile memories for neuromorphic and fast computing applications, new innovative device designs for high-density charge trapping memories are required [3].…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory

Ansari

El‐Atab

2022

2022 IEEE Silicon Nanoelectronics Workshop (SNW)

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This work presents vertically stackedNanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 µs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same E ox .

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Section: Introductionmentioning

confidence: 99%

Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory

Ansari

El‐Atab

2022

2022 IEEE Silicon Nanoelectronics Workshop (SNW)

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“…NAND technology currently uses a three-dimensional (3-D) structure and polysilicon as the channel material [4]. However, when implementing multi-level technology and high-rise stacking technology to enhance efficiency, several factors affect the variability of 3-D NAND flash memories, and these factors can be classified into three categories [5]: the effect of grain boundary traps [6][7][8][9], fluctuations in the control of the critical dimension [10], and the effect of the tapered channel [11][12][13]. Among these factors, the taper angle and the mold height are major reasons for the string performance differences between the top and the bottom cells as the number of cells is increased.…”

Section: Introductionmentioning

confidence: 99%

Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

Lee

Jung

Park

et al. 2021

IEEE J. Electron Devices Soc.

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The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (∆VT) between the cells. The difference in ∆VT between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories. Index Terms-3-D NAND flash memories, threshold voltage shift, tapered channel

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