On pinpoint capture power management in at-speed scan test generation

Wen, Xiaoqing; Nishida, Yuya; Miyase, Kohei; Kajihara, Seiji; Girard, Patrick; Tehranipoor, Mohammad; Wang, L.-T.

doi:10.1109/test.2012.6401548

Cited by 25 publications

(26 citation statements)

References 17 publications

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“…The instantaneous impact of excessive capture power is significant delay increase, which may cause test responses to be incorrectly captured at the end-points of some sensitized paths at T 2 , leading to over-kill-induced yield loss (i.e., failing good chips). Therefore, test power safety, including both shift power safety and capture power safety, need to be guaranteed in order to conduct scan testing [10]- [12] successfully, in the form of both stored pattern testing and logic BIST.…”

Section: Importance Of Test Power Safetymentioning

confidence: 99%

“…• Toward Capture Power Safety A typical capture-power-safe solution for stored pattern testing is rescue-&-masking [11], [12], in which (1) the local switching activity around each long sensitized path (LSP) of a test vector is checked to determine if it is a risky path (i.e., an LSP whose surrounding switching activity is so high that the test response from the LSP is possibly-erroneous as an uncertain value); (2) for any risky path, X-filling [17] is conducted in a pinpoint manner to directly reduce its surrounding switching activity; (3) if the effect of switching activity reduction is insufficient to turn a risky path into a non-risky path, the uncertain test response from the risky path will be masked to instruct the tester not to use it. This way, any adverse impact of excessive capture power on final test results is avoided, thus realizing capture power safety.…”

Section: • Toward Shift Power Safetymentioning

confidence: 99%

“…These paths are risky paths (e.g., P in Fig. 2) since test responses from them are possibly-erroneous (i.e., test response values become uncertain) [11], [12]. At T 2 (also shown in Fig.…”

Section: Capture Power Safety Problem In Logic Bistmentioning

confidence: 99%

“…1). It is obvious that a long sensitized path (LSP) is vulnerable to such timing impact of excessive capture power [11], [12], [20]. Thus, capture power safety checking is preferably conducted with a LSP-based approach based on the following definitions [11], [12]:…”

Section: Lsp-based Capture Power Safety Checkingmentioning

confidence: 99%

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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

Tomita

Wen

Suzuki

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYThe applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slicemasking, vector-masking) to block them from reaching the multiple-input signature register (MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead. key words: at-speed scan-based logic BIST, capture power safety, masking, IR-drop, transition delay fault, long sensitized path

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Section: Importance Of Test Power Safetymentioning

confidence: 99%

Section: • Toward Shift Power Safetymentioning

confidence: 99%

“…These paths are risky paths (e.g., P in Fig. 2) since test responses from them are possibly-erroneous (i.e., test response values become uncertain) [11], [12]. At T 2 (also shown in Fig.…”

Section: Capture Power Safety Problem In Logic Bistmentioning

confidence: 99%

Section: Lsp-based Capture Power Safety Checkingmentioning

confidence: 99%

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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

Tomita

Wen

Suzuki

et al. 2014

IEICE Trans. Inf. & Syst.

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“…Together with several benefits (improved performance, decreased cost per function, etc. ), this poses serious challenges in terms of test and reliability [1,2,3,4,5,6,7]. In particular, during at-speed test of high performance microprocessors, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during in field operation [5,8,9,11,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Omaña

Rossi

Fuzzi

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel, scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the Logic BIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target Fault Coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared to recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

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Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Eggersglüβ

2014

J Electron Test

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Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic Xfilling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.

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On pinpoint capture power management in at-speed scan test generation

Cited by 25 publications

References 17 publications

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

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