Program/Erase Cycling Degradation Mechanism of HfO<sub>2</sub>-Based FeFET Memory Devices

Zeng, Binjian; Liao, Min; Liao, Jiajia; Xiao, Wenwu; Peng, Qiangxiang; Zheng, Shuaizhi; Zhou, Yue

doi:10.1109/led.2019.2908084

Cited by 56 publications

(36 citation statements)

References 17 publications

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“…Stress is induced by positive and negative pulses applied on the gate to erase and program the FeFET, respectively. Hence, V th,on tends to decrease and V th,o f f to increase 21 . The concentration of generated defects during writing of the memory is in general different depending on the sign of the writing pulse, therefore the shifts in V th,on and V th,o f f are not symmetric.…”

mentioning

confidence: 96%

“…Symbols: Exp. Data Lines: Analytical it takes for a single writing cycle is t cycle = 200ns 21 . The variation in V th,on and V th,o f f is in turn reflected to the MW , as shown in Fig.…”

mentioning

confidence: 99%

“…The good agreement between analytical and experimental results in Figs. 1 and 2 was obtained by extracting the generated oxide and interface trap concentrations from ∆V th,on and ∆V th,o f f data in 21 following the approach described in 26 . That is, N ot and D it were extracted by separating the threshold voltage shifts due to oxide (∆V mg ) and interface traps (∆V it ) separately.…”

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confidence: 99%

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A memory window expression to evaluate the endurance of ferroelectric FETs

Zagni

Pavan

2020

Applied Physics Letters

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The recent discovery of ferroelectricity in HfO2 has revived the interest into non-volatile memories based on ferroelectric transistors (FeFETs). The key advantages of these FeFETs include the low power consumption and the compatibility with the existing CMOS process. On the other hand, issues related mainly to endurance still represent a challenge to the development of the technology. In this Letter, we propose to exploit an analytical expression for the Memory Window (MW) as a simple yet effective characterization tool to evaluate the endurance of FeFETs. The MW is defined as the difference between threshold voltages occurring due to polarization switching. The analytical formulation of the MW allows one to quickly estimate the generated trap concentration as a function of number of writing cycles (or time) without recurring to numerical simulations. With the aid of the analytical model, we find that for typical program/erase pulse amplitudes and duration, endurance has a weak dependence on writing conditions. The characterization technique based on the MW would allow the systematic comparison of the performance and endurance of next-generation FeFETs.

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mentioning

confidence: 96%

“…Symbols: Exp. Data Lines: Analytical it takes for a single writing cycle is t cycle = 200ns 21 . The variation in V th,on and V th,o f f is in turn reflected to the MW , as shown in Fig.…”

mentioning

confidence: 99%

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confidence: 99%

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A memory window expression to evaluate the endurance of ferroelectric FETs

Zagni

Pavan

2020

Applied Physics Letters

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“…The pulse voltage of the program/erase (PGM/ERS) process causes a strong electric field to be applied to the very thin HfO 2 thin film, which reduces endurance. In addition, it is known that trapped charges appearing at the interface during the PGM and ERS processes reduce data retention [113,114]. However, even if the reduction of endurance at the interface is solved, this does not solve the fundamentally low endurance of 10 7 , so new structure and methods must be introduced, such as the introduction of MFMIS structure or subloop driving.…”

Section: Ferroelectric Field-effect Transistor (Fefet)mentioning

confidence: 99%

Ferroelectrics Based on HfO2 Film

Song

Kwon

2021

Electronics

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The discovery of ferroelectricity in HfO2 thin film, which is compatible with the CMOS process, has revived interest in ferroelectric memory devices. HfO2 has been found to exhibit high ferroelectricity at a few nanometers thickness, and studies have rapidly progressed in the past decade. Ferroelectricity can be induced in HfO2 by various deposition methods and heat treatment processes. By combining ferroelectric materials with field-effect transistors, devices that combine logic and memory functions can be implemented. Ferroelectric HfO2-based devices show high potential, but there are some challenges to overcome in endurance and characterization. In this paper, we discuss the fabrication and characteristics of ferroelectric HfO2 film and various applications, including negative capacitance (NC)), Ferroelectric random-access memory (FeRAM), Ferroelectric tunnel junction (FTJ), and Ferroelectric Field-effect Transistor (FeFET).

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“…Therefore, it is essential to minimize the influence of the degradation of the FeFET to stably store the data. For this purpose, the understanding of degradation mechanism of the FeFET according to PG/ER cycling has been studied [17], [18].…”

Section: Introductionmentioning

confidence: 99%

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Min

Ronchi

McMitchell

et al. 2021

IEEE Electron Device Lett.

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The endurance of the HfO2-based ferroelectric FET (FeFET) is investigated using various program/erase (PG/ER) pulse schemes. The ramp time (Tramp), which is the time to reach the PG/ER voltage, and the hold time (Thold), which is the time duration to maintain the PG/ER voltage, are adjusted, and thereafter, their influence on endurance is observed through the memory window, subthreshold slope, and threshold voltage of the FeFET while the FeFET is cycled up to 10 4 by a sequence of PG/ER pulses. Both parameters are closely related to depassivating interface traps, and it turns out that a long Tramp but short Thold are desirable to suppress the interface trap generation in FeFET. The relation between Tramp, Thold and the interface trap generation is explained by the transient built-in electric field (which is generated by the transiently trapped carrier in the gate oxide when the gate voltage is swept rapidly).

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Program/Erase Cycling Degradation Mechanism of HfO₂-Based FeFET Memory Devices

Cited by 56 publications

References 17 publications

A memory window expression to evaluate the endurance of ferroelectric FETs

A memory window expression to evaluate the endurance of ferroelectric FETs

Ferroelectrics Based on HfO2 Film

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

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Program/Erase Cycling Degradation Mechanism of HfO2-Based FeFET Memory Devices

Cited by 56 publications

References 17 publications

A memory window expression to evaluate the endurance of ferroelectric FETs

A memory window expression to evaluate the endurance of ferroelectric FETs

Ferroelectrics Based on HfO2 Film

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor

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Program/Erase Cycling Degradation Mechanism of HfO₂-Based FeFET Memory Devices

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor