Robust Protection Device for Electrostatic Discharge/Electromagnetic Interference in Industrial Interface Applications

Xi, Yunfeng; Salcedo, Javier A.; Dong, Aihua; Liou, Juin J.; Hajjar, Jean-Jacques

doi:10.1109/tdmr.2016.2530701

Cited by 7 publications

(4 citation statements)

References 5 publications

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“…The trigger voltage of traditional DDSCR with a highly doped P+ structure is 22.471 V and the sustain voltage is 19.156 V, while the trigger voltage of DDSCR with a low doping deep well PB structure is 28.638 V and the sustain voltage is 20.093 V. Both the conventional DDSCR structure and the deep well DDSCR structure have an index length of 100 μm and an index of 8. Therefore, according to the calculation formula [5], the FOM of the conventional DDSCR is 0.0057, and the FOM of the deep well DDSCR is 0.0071.…”

Section: Resultsmentioning

confidence: 99%

“…With the development of IC manufacturing process and the miniaturization of semiconductor devices, more and more engineers choose the SCR devices with the best robustness per unit area of ESD protection in order to reach higher efficiency for integrated circuits. Therefore, the dual direction SCR is applied to the Bus interface's A/B port to prevent the forward and reverse ESD stress from damaging the chip [1][2][3][4][5]. The communication bus has a transfer rate of 250-kbps and is a low-speed application.…”

Section: Introductionmentioning

confidence: 99%

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Dual direction SCR with deep well structure for high voltage ESD in communication bus

Wang

Jin

Zheng

et al. 2019

Semicond. Sci. Technol.

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In order to improve the robustness of the ESD of the dual-direction silicon-controlled rectifier, a low doping deep well PB structure is proposed instead of the traditional high doping P+ structure. The ESD stress of the dual-direction SCR devices with deep well structure is discharged from inside and the lattice temperature of the device is low to avoid premature burnout of the device. The deep well PB structure on the surface of the device increases the parasitic resistance of the device and improve the conduction uniformity of the device. As the main conduction path of the device is located in NBL, the PB structure does not have a large influence on the sustain voltage. It is verified in a 0.25 μm BCD process. With equivalent circuit and two-dimensional device simulation, the working mechanism is analyzed. According to the transmission line pulse test results and comparing with the data from traditional dual-direction SCR structure. The device's fault current increases from 5.486 A to 8.13 A which is suitable for communication bus high voltage electrostatic discharge (ESD) protection.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Dual direction SCR with deep well structure for high voltage ESD in communication bus

Wang

Jin

Zheng

et al. 2019

Semicond. Sci. Technol.

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“…Conventional diode structures and Gate-Grounded NMOS (GGNMOS) structures always require a large silicon area to achieve a good ESD robustness [7][8][9][10]. By contrast, silicon controlled rectifiers (SCRs) have been widely used due to their highest robustness per unit area [11][12][13][14][15][16][17][18][19][20]. However, the unique positive feedback loop of the SCR structure makes it have deep snapback characteristics, which cause a low holding voltage.…”

Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

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The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (Vh). Two GC-DDSCRs are fabricated in a 0.5μm CMOS technology and tested by transmission line pulse (TLP). The Vh increases from 13.84V to 16.44V as the gate size expands from 2.5μm to 4.5μm. The mechanism of current aggregation is verified.

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“…The results show that the device has good anti-electromagnetic interference capability and ESD release capability. It can be applied to industrial interfaces of -7V~12V [7]. Hu et al proposed a novel SCR device with double snapback capability by embedding a grounded-gate N-type metal-oxide semiconductor (GGNMOS) structure on the SCR, and the current release capability of the device reached 33 mA/μm.…”

Section: Introductionmentioning

confidence: 99%

Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

et al. 2020

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Robust Protection Device for Electrostatic Discharge/Electromagnetic Interference in Industrial Interface Applications

Cited by 7 publications

References 5 publications

Dual direction SCR with deep well structure for high voltage ESD in communication bus

Dual direction SCR with deep well structure for high voltage ESD in communication bus

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

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