Single‐chip processor for media applications: the MAP1000™

Basoglu, Chris; Gove, Robert; Kojima, Keiji; O’Donnell, J. M.

doi:10.1002/(sici)1098-1098(1999)10:1<96::aid-ima11>3.3.co;2-x

Cited by 10 publications

(8 citation statements)

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“…Such ohmic bistable nanodevices were recently demonstrated using phase change in thin chalcogenide bridges [43]. 8 The digital implementation discussed in the previous section is also parallel for all output pixels (i.e., all values of r fx; yg); however it is time-serial for the filter window pixels (numbered by index k fi; j g).…”

Section: Mixed-signal Optionmentioning

confidence: 99%

“…1 Instead, the most promising computational platforms in this field are digital signal processors (DSPs) [7], [8], field programmable gate arrays (FPGAs) [9], [10], and most notably, focal-plane processor arrays with digital [11] or analog [12]- [14] cores. The basic idea of focal plane processor arrays is to integrate the signal processing circuitry with sensor devices, so that all the data from sensors are processed locally, with no resources wasted for long-distance data transfer.…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

Strukov

Likharev

2007

IEEE Trans. Nanotechnology

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We have analyzed two options of using hybrid CMOS/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the analog presentation of input and output data and the binary presentation of the filter function. Estimates of the circuit performance have been carried out for the 45-nm CMOS technology and the 4.5-nm nanowire half-pitch, and the power consumption fixed at a manageable, ITRS-specified level. In the digital case, the circuit area per pixel is about 25 25 m 2 , and the time necessary for convolving a 1024 1024-pixel, 12-bit-accurate image with a 32 32-pixel window function of similar accuracy is close to 25 s, much shorter than that estimated for purely CMOS circuits with the same minimum feature size on 45 nm. For a mixed-signal CMOL circuit, the corresponding numbers are much better ( 1 m 2 and 1 s, respectively), but this option requires a very high ( 1%) reproducibility of ON currents of the necessary crosspoint devices (programmable diodes), which has not yet been reached experimentally.

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Section: Mixed-signal Optionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

Strukov

Likharev

2007

IEEE Trans. Nanotechnology

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“…3 Figure 5 shows its highlevel block diagram where the core processor block consists of two clusters, a 16-kbyte four-way set-associative data cache, and a 16-kbyte two-way set-associative instruction cache. It has an on-chip programmable DMA controller called data streamer ͑DS͒.…”

Section: Implementation On the Map1000mentioning

confidence: 99%

“…To meet this increasing computing demand at an affordable cost, new advanced digital signal processors ͑DSPs͒ known as media processors have been emerging, typically with a very long instruction word ͑VLIW͒ architecture, e.g., Texas Instruments TM320C80, 1 Philips Trimedia TM1000, 2 and Hitachi/Equator Technologies MAP1000. 3 A media processor typically has several arithmetic units and load/store units, which can operate concurrently. Many arithmetic units can support partitioned operations, e.g., a 64-bit computing engine can be divided into eight 8-bit units to perform eight operations in parallel.…”

Section: Introductionmentioning

confidence: 99%

Mapping of two-dimensional convolution on very long instruction word media processors for real-time performance

Managuli

York

Kim

et al. 2000

J. Electron. Imaging

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Programmable media processors have been emerging to meet the continuously increasing computational demand in complex digital media applications, such as HDTV and MPEG-4, at an affordable cost. These media processors provide the flexibility to implement various image computing algorithms along with high performance, unlike the hardwired approach that has provided high performance for a particular algorithm, but lacks flexibility. However, to achieve high performance on these media processors, a careful and sometimes innovative design of algorithms is essential. In addition, programming techniques, e.g., software pipelining and loop unrolling, are needed to speed up the computations while the data flow can be optimized using a programmable DMA controller. In this paper, we describe an algorithm for two-dimensional convolution, which can be implemented efficiently on many media processors. Implemented on a new media processor called the MAP1000, it takes 7.9 ms to convolve a 512ϫ512 image with a 7ϫ7 kernel, which is much faster than the previously reported software-based convolution and is comparable with the hardwired implementations. High performance in two-dimensional convolution and other algorithms on the MAP1000 clearly demonstrates the feasibility of software-based solutions in demanding imaging and video applications. © 2000 SPIE and IS&T. [S1017-9909(00)

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“…Efforts to process multiple types of multimedia data with a single processor have resulted in media processors. Typical examples are the MAP, MAP-CA [15], and TriMedia [16] processors. MAP processors use a VLIW architecture with a large instruction set and special functional units tuned to perform common image processing kernels in hardware [15].…”

Section: Introductionmentioning

confidence: 99%

PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

Lee

Fiskiran

2005

J VLSI Sign Process Syst Sign Image Video Technol

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PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms.Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLX's wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through interinstruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.

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Single‐chip processor for media applications: the MAP1000™

Cited by 10 publications

References 0 publications

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

Mapping of two-dimensional convolution on very long instruction word media processors for real-time performance

PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

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