Timing-Aware Power-Noise Reduction in Placement

Abstract

In this paper, we describe a placement-level decap insertion technique whose objective is to reduce power-noise, taking into account circuit timing. Our approach consists of prediction and correction steps. Before placement, we estimate the power noise of each cell considering switching frequency of cells which, after placement, will most likely be in the neighborhood. If a frequently switching cell has neighbors that switch infrequently, it is unlikely that this cell will suffer from a power noise problem. Based on the cell power noise estimation, we add decap padding to each cell. Then we invoke a standard cell placement tool and perform power grid analysis. We eliminate the power grid noise by gate sizing. Our technique can allocate decaps to improve power noise, power consumption, and timing. We propose two gate-sizing algorithms. The first one uses a Sequence of Linear Programs (SLP) formulation, and the second one uses a budgeting-based heuristic algorithm. The SLP algorithm can produce better power noise results than the heuristic, at the expense of run time. Experimental results show that our techniques can effectively reduce power noise and still meet timing constraints.

Decoupling capacitor planning with analytical delay model on RLC power grid

“…Thus, we repeat this iterative LP minimization and floorplan expansion until our objective becomes zero, therefore, the decap demand is satisfied. 3 Constraints (12) and (13) in this LP are identical to Equations (8) and (9).…”

“…3 The total number of iterations depends on the noise constraint and the initial floorplan. Our experimental results show the amount of expansion needed for each circuit in Section IV-B.…”

“…In addition, our analytical model captures the highly non-linear relation between delay and decap. The work in [3] considers both power-supply noise and delay minimization in gate-level placement. Their delay model is related to the voltage change by a non-linear function.…”

Gate delay estimation in STA under dynamic power supply noise

“…Decoupling capacitance insertion is a well-known and effective way to suppress power supply noise [5]. Conventionally, it is inserted to satisfy constraints in noise voltage, and it has not been directly associated with timing except a few papers such as [6], since the timing estimation that takes into account dynamic voltage drop has not been well established.…”

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance

“…Several factors such as the placement, size, and recharge time of the decoupling capacitors should be considered for efficiency [11]- [13]. Another important consideration for decoupling capacitors is the resonance.…”