TMT: A TLB Tag Management Framework for Virtualized Platforms

Venkatasubramanian, Girish; Figueiredo, Renato; Illikkal, Ramesh; Newell, Don

doi:10.1007/s10766-011-0189-y

Cited by 4 publications

(7 citation statements)

References 19 publications

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“…Wiggins et al [2003] propose a software method to maintain process ID for TLB entry. Venkatasubramanian et al [2009] show that TLB management overhead is one of the most significant performance bottlenecks in multicore-based VMs and recommend separate tagged TLB for individual virtual platforms.…”

Section: Related Workmentioning

confidence: 97%

SmartCon

et al. 2015

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Handling of storage IO in modern operating systems assumes that such devices are slow and CPU cycles are valuable. Consequently, to effectively exploit the underlying hardware resources, for example, CPU cycles, storage bandwidth and the like, whenever an IO request is issued to such device, the requesting thread is switched out in favor of another thread that may be ready to execute. Recent advances in nonvolatile storage technologies and multicore CPUs make both of these assumptions increasingly questionable, and an unconditional context switch is no longer desirable. In this article, we propose a novel mechanism called SmartCon, which intelligently decides whether to service a given IO request in interrupt-driven manner or busy-wait-based manner based on not only the device characteristics but also dynamic parameters such as IO latency, CPU utilization, and IO size. We develop an analytic performance model to project the performance of SmartCon for forthcoming devices. We implement SmartCon mechanism on Linux 2.6 and perform detailed evaluation using three different IO devices: Ramdisk, low-end SSD, and high-end SSD. We find that SmartCon yields up to a 39% performance gain over the mainstream block device approach for Ramdisk, and up to a 45% gain for PCIe-based SSD and SATA-based SSDs. We examine the detailed behavior of TLB, L1, L2 cache and show that SmartCon achieves significant improvement in all cache misbehaviors.

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Section: Related Workmentioning

confidence: 97%

SmartCon

et al. 2015

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“…Venkatasubramanian et al note that workload consolidation through virtualization increases the number of distinct VA spaces and the context switche frequency between them. Because context switch requires flushing the TLB, virtualization can increase TLB flushes by 10 × and miss rate of DTLB and ITLB by 5 × and 70 × , respectively.…”

Section: Techniques For Improving Tlb Coverage and Performancementioning

confidence: 99%

“…Similarly, virtual caches can be used to reduce TLB accesses. TLB leakage energy can be reduced by using reconfiguration and using non‐volatile (ie, low‐leakage) memory to design TLB TLB miss‐rate can be lowered by increasing TLB reach (eg, by using superpages or variable page‐size), by using prefetching, software caching, TLB partitioning and reducing flushing overhead (Table ). Some techniques use tags (eg, ASID) to remove homonyms and/or reduce flushing overhead Because stack and heap and global‐static, and private and shared data show different characteristics, utilizing this semantic information and page classification information (respectively) allows design of effective management techniques (Table ). Because ITLB miss‐rate is generally much lower than that of DTLB, some researchers focus only on DTLB .…”

Section: Background and Overviewmentioning

confidence: 99%

A survey of techniques for architecting TLBs

Mittal

2016

Concurrency and Computation

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Summary Translation lookaside buffer (TLB) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high‐end servers. Because TLB is accessed very frequently and a TLB miss is extremely costly, prudent management of TLB is important for improving performance and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and managing TLBs. We characterize the techniques across several dimensions to highlight their similarities and distinctions. We believe that this paper will be useful for chip designers, computer architects, and system engineers.

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“…Tickoo et al [12] and Venkatasubramanian et al [13] have investigated TLB tagging with domain 1 -specific and processspecific tags. However, the limitation of these studies is that the metric used for evaluating the impact of TLB tagging is miss rate and not timing-based metrics.…”

Section: Related Workmentioning

confidence: 99%

“…Beyond 256 entries, the dominant cause for TLB misses is the repeated flushing of the TLB and not TLB size limitations. From earlier work [13], it is known that the ITLB and DTLB miss rates for TPCC-UVa reduce on scaling up the TLB size till 256 entries and remain constant for larger sizes. It can be seen from Figure 4a, that a similar trend is exhibited in the TLB R IP C values.…”

Section: A Effect Of Virtualization On Tlb's Impact On Workload Perfmentioning

confidence: 99%

A Simulation Framework for the Analysis of the TLB Behavior in Virtualized Environments

Venkatasubramanian

Figueiredo

Illikkal

et al. 2010

2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems

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Due to the rising importance of virtualization, extensive efforts have gone into determining and improving the performance of workloads on virtualized platforms. This has resulted in a series of modifications to the leading architecture used in virtualized systems (x86) by adding hardware support for virtualization, the latest of which is the addition of tags and tag comparators to the x86 TLB. In this context, it is necessary to have a thorough understanding of the TLB behavior of virtualized workloads and understand the change in this behavior with TLB related architectural parameters. One way of obtaining this understanding is by conducting a simulation-based study of the interaction of various microarchitectural parameters and their effect on the TLB behavior. However, the lack of suitable simulation frameworks makes such a study daunting.In this paper, we present a full-system simulation framework which is suitable for conducting such studies. We first motivate the need for TLB modeling in virtualized systems. Then, we present the framework, develop and validate a timing model for the TLB and evaluate the simulation speed when this model is used. Using the timing model, the influence of the TLB on workload performance is examined for a variety of single and multi-domain workloads and compared with equivalent non-virtualized workloads. It is found that the performance of virtualized workloads, in terms of instructions per cycle (IPC), can vary by 1% to 35% due to the TLB and that this IPC variation can be as much as 9 times the variation in nonvirtualized workloads.

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TMT: A TLB Tag Management Framework for Virtualized Platforms

Cited by 4 publications

References 19 publications

SmartCon

SmartCon

A survey of techniques for architecting TLBs

A Simulation Framework for the Analysis of the TLB Behavior in Virtualized Environments

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