Top-down RSFQ logic design based on a binary decision diagram

Yoshikawa, Nobuyuki; Koshiyama, Junichi

doi:10.1109/77.919539

Cited by 31 publications

(18 citation statements)

References 7 publications

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“…In the previously proposed BDD SFQ circuits, we have implemented BDD nodes by using one-to-two binary switch gates [3]. More diagram of these gates are shown in Fig.…”

Section: Bdd Sfq Logic Circuitsmentioning

confidence: 99%

“…2. The Bina is a resettable, destructive read-out D flip-flop with complementary outputs [3]. The ndroc is resettable, nondestructive read-out D flip-flop with complementary putouts [5].…”

Section: Bdd Sfq Logic Circuitsmentioning

confidence: 99%

“…The BDD is a way to represent a logical function by a directed graph, which is composed of nodes having one input and two outputs [3]. The node switches an input signal into one of the two outputs depending on its internal state.…”

Section: Bdd Sfq Logic Circuitsmentioning

confidence: 99%

“…One solution to overcome the timing issue is the introduction of an asynchronous design approach that eliminates a global clock for individual logic gates [2]. We have proposed an asynchronous design approach based on the binary decision diagram (BDD) for SFQ circuits and shown its validity previously [3]. The BDD SFQ logic style is now used in the design of circuit blocks of recent large-scale SFQ circuits.…”

Section: Introductionmentioning

confidence: 99%

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Advanced Design Approaches for SFQ Logic Circuits Based on the Binary Decision Diagram

Nishigai

Ito

Yoshikawa

et al. 2005

IEEE Trans. Appl. Supercond.

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We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented by using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA cm 2 Nb standard process and the CONNECT cell library.The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip highspeed tests.

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“…In the previously proposed BDD SFQ circuits, we have implemented BDD nodes by using one-to-two binary switch gates [3]. More diagram of these gates are shown in Fig.…”

Section: Bdd Sfq Logic Circuitsmentioning

confidence: 99%

“…2. The Bina is a resettable, destructive read-out D flip-flop with complementary outputs [3]. The ndroc is resettable, nondestructive read-out D flip-flop with complementary putouts [5].…”

Section: Bdd Sfq Logic Circuitsmentioning

confidence: 99%

Section: Bdd Sfq Logic Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Advanced Design Approaches for SFQ Logic Circuits Based on the Binary Decision Diagram

Nishigai

Ito

Yoshikawa

et al. 2005

IEEE Trans. Appl. Supercond.

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“…We have proposed a cell-based design approach [3] based on a binary decision diagram (BDD) [4] and made a BDD SFQ standard cell library [5]. A top-down CAD environment [6] is also developed to assist the large-scale circuit design.…”

Section: Introductionmentioning

confidence: 99%

Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

Yoshikawa

Yoda

Hoshina

et al. 2003

IEEE Trans. Appl. Supercond.

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We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and don't need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. In the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.Index Terms-Binary decision diagram, cell base design, cell library, RSFQ, superconducting circuits.

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EDA for Superconductive Electronics

Krylov

Friedman

2021

Single Flux Quantum Integrated Circuit Design

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Top-down RSFQ logic design based on a binary decision diagram

Cited by 31 publications

References 7 publications

Advanced Design Approaches for SFQ Logic Circuits Based on the Binary Decision Diagram

Advanced Design Approaches for SFQ Logic Circuits Based on the Binary Decision Diagram

Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

EDA for Superconductive Electronics

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