Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical efect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 14 noise. The technique is implemented in a 0 . 8 p CMOS sawtooth oscillator by periodically of-switching of the bias currents during time intervals that theyare not contributing to the circuit operation. Measurements show a reduction of the lynoise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

A new measurement setup is presented that allows the observation of 1 noise spectra in MOSFET's under switched bias conditions in a wide frequency band (10 Hz-100 kHz). When switching between inversion and accumulation, MOSFET's of different manufacturers invariably show reduced 1 noise power density for frequencies below the switching frequency. At low frequencies (10 Hz), a 5-8 dB reduction in intrinsic 1 noise power density is found for different devices, largely independent of the switching frequency (up to 1 MHz). The switched bias measurements render detailed wideband 1 noise spectra of switched MOSFET's, which is useful for 1 noise model validation and analog circuit design.

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1=f noise and hence the oscillator's close-in phase noise. More specifically, it is shown that the 1=f 3 phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1=f 3 phase noise than expected. It will be shown that this can be attributed to the intrinsic 1=f noise reduction effect due to periodic on-off switching.

In this paper, we present measurements and simulation of random telegraph signal (RTS) noise in n-channel MOS-FETs under periodic large signal gate-source excitation (switched bias conditions). This is particularly relevant to analog CMOS circuit design where large signal swings occur and where LF noise is often a limiting factor in the performance of the circuit. Measurements show that, compared to steady-state bias conditions, RTS noise can decrease but also increase when the device is subjected to switched bias conditions. We show that the simple model of a stationary noise generating process whose output is modulated by the bias voltage is not sufficient to explain the switched bias measurement results. Rather, we propose a model based on cyclostationary RTS noise generation. Using our model, we can correctly model a variety of different types of LF noise behavior that different MOS-FETs exhibit under switched bias conditions. We show that the measurement results can be explained using realistic values for the bias dependency of and .

In this work, we study random telegraph signal ͑RTS͒ noise in metal-oxide-semiconductor field effect transistors when the device is periodically and rapidly cycled between an "on" and an "off" bias state. We derive the effective RTS time constants for this case using Shockley-Read-Hall statistics applied under transient conditions. In this way, we show that the oft-observed reduction in RTS noise under such bias conditions can be explained by a nonuniform ͑e.g., U-shaped͒ distribution in energy of interface traps.