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As semiconductor device features shrink into deep-submicron regime, copper metallization is taking the place of aluminum (Al)-tungsten (W) metallization because of the higher electrical conductivity and electromigration resistance of copper. However, it is very difficult for copper to be etched by dry etching method, thus copper metallization is created with damascene process. In this process, chemical mechanical polishing (CMP) is the key step. The wet chemical treatment in CMP makes copper corrosion to be one of the critical issues for copper metallization. This paper has addressed the three different types of copper corrosion, namely copper chemical corrosion, copper galvanic corrosion and photo assistant copper corrosion. The failure analyses for how to differentiate them and identify their root causes have been also discussed in details.

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There are several methods commonly used to locate the area of interest (AOI), such as using layout landmarks, applying laser marks, focus ion beam marks, etc. This paper discusses another method which can improve the job efficiency and cost-effectiveness by introducing the combination of laser marking and laser deprocessing technique (LDT) as a quick way to deprocess the AOI. It further explores LDT to improve the job efficiency and throughput in logic devices to achieve cost-saving targets. An experiment was performed on a 14nm technology node prototype chip that integrated logic and SRAM. The proposed LDT has demonstrated itself to be a useful method to increase the job efficiency by performing in batch and easy to locate the AOI upon loading the sample for SEM inspection. It is also a simple and cost-effective way to delayer comparing to other methodologies.

Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.