Defect evolution in ion implanted c-Si at the submicrosecond time scales during a laser thermal annealing process is investigated by means of kinetic simulations. Nonmelting, melting, and partial melting regimes are simulated. Our modeling considers irradiation, heat diffusion, and phase transition together with defect diffusion, annihilation, and clustering. The reduction in the implantation damage and its reorganization in defect aggregates are studied as a function of the process conditions. The approach is applied to double implanted Si and compared to experimental data, indicating a relationship between damage reduction and dopant activation.

Processes using laser-shock applications, such as Laser Shock Peening or Laser Stripping require a deep understanding of both mechanical and thermal loading applied. We hereby present new experimental measurements of the plasma pressure release regarding its initial dimension, which depends on the laser beam size. Our data were obtained through shock waves' velocity analysis and radiometric assessments. A new model to describe the adiabatic release behavior of a laser-induced plasma with a dependency to the beam size is developed. The results and the associated model exhibit that the plasma release duration is shortened with smaller laser spots. As a consequence, with chosen smaller laser spots (0.6 mm to 1 mm), the thermal loading applied during the plasma lifetime will also decrease. These new results shall help for a better understanding of laser-matter interaction for laser-shock applications by giving more accurate plasma profiles. Thus, process simulations can be improved as well. Eventually, by considering recent developments with high-power Diode Pumped Solid-State lasers (DPSS), we now expect to develop a new configuration for LSP which could be applicable both without any thermal coating and deliverable by an optical fiber.

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With the growing demand for improved performance, increased storage capacity and more functionality, the industry is facing challenges which require disruptive solutions. With the introduction of 3D geometries (e.g. FinFET) and of active layer stacking (e.g. sensors), annealing of 3D architectures is a major challenge for future generation devices. The drive towards lower power consumption and better thermal management leads to the integration of alternatives to Si, materials for which the thermal budget has to be carefully controlled, e.g. Ge and III-Vs for logic or SiC and GaN for power devices. A promising approach is Laser Thermal Annealing (LTA), an ultrafast and low thermal budget process in production for the passivation of backside illuminated sensors and power devices. The high temperature annealing region is restricted to thin layers while keeping underlying layers at low temperature. An ultrafast annealing time and proper Laser parameters may achieve high performance and high yield process, locking-in the surface properties without damaging buried device layers. We present here a review of LTA applications including recent work in memory.