We report the fabrication of a 0.12 µm T-gate with a silicon nitride assisted process. A two-step etch process was performed to define the gate footprint in the SiN x . The SiN x was etched either by dry etching (RIE) alone or by using a combination of wet and dry etching. The gate recessing was done in two steps including a wet etching for the removal of the damaged surface layer and a dry etching for the narrow recess. We have seen that the increases of the cut-off frequency f T and the maximum oscillation frequency f max are 39% and 16%, respectively. This was believed to be due to a remarkable decrease of the gate-source and gate-drain capacitances by 25% and 18.3%, respectively. The improvement in RF performance can be understood in terms of the decrease in parasitic capacitances due to SiN x and the gate recess etching method.

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We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric‐defined process. This process was utilized to fabricate 0.12 μm × 100 µm T‐gate PHEMTs. A two‐step etch process was performed to define the gate footprint in the SiNx. The SiNx was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T‐gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross‐sectional area of the gate and its mechanically stable structure. From s‐parameter data of up to 50 GHz, an extrapolated cut‐off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the SiNx) with sample A (dry etching for the SiNx), we observed an 62.5% increase of the cut‐off frequency. This is believed to be due to considerable decreases of the gate‐source and gate‐drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

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