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Advanced wafer-level packaging (WLP) techniques, mainly driven by high-performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology have been widely studied and developed over the last decade for use in various WLP technologies, such as package on package, fan-out integration, and 2.5-D and 3-D integration using through-silicon-via. Temporary bonding technology enables handling of thinned substrates (<100 μm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics was developed for temporary wafer bonding applications. These materials target high-temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (<5 μm) after grinding and have successfully passed a 200°C plasma-enhanced chemical vapor deposition (PECVD) process without any delamination during grinding and PECVD processes.

Interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and the substrate [1]. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE as well as the ability to provide a low cost solution [2].In this investigation, another cost reduction concept of through glass via (TGV) wafer processing is being studied. By leveraging current semiconductor equipment and knowhow, we bond TGV wafers onto glass carriers as shown in Figure 1, the TGV wafer thickness is directly 100um and center diameter (CD) of through glass via is 30 m. This approach provides a method to temporarily bond these TGV wafers to glass carriers enabling handling through processes such as via fill and surface metallization. The ability to form glass at the target 100 um thickness and provide through holes and thus avoid backgrinding processes provides substantial opportunity to save costs and avoid yield loss.