A novel integrated gate driver with bi-scanning structure using a-Si TFT for large size FHD TFT-LCD TV has been developed. The proposed gate driver has bi-scan control circuit which enables reverse scanning operation and TFT stress reduction circuit which enhances gate driver reliability for TV application. Two channel shared node structure also reduce the area of the circuit without performance degradation, while the life time of the integrated gate driver is estimated to 100,000 hours. Thus we successfully developed 47 inch FHD 120Hz TFT-LCD panel with this integrated gate driver circuit using a-Si TFT.
An excess oxygen‐peroxide‐based model that can simultaneously analyze the positive‐bias‐stress (PBS) and negative‐bias‐illumination‐stress (NBIS) instabilities in commercial self‐aligned top‐gate (SA‐TG) coplanar indium–gallium–zinc oxide (IGZO) thin‐film transistors (TFTs) is proposed herein. Existing studies have reported that the transition of oxygen vacancy (VO) charge states from VO0 to VO2+ is the dominant physical mechanism responsible for the negative shift of threshold voltage (VTH) under NBIS. However, in this study, it is observed that both the PBS and the NBIS stabilities of IGZO TFTs deteriorate at a faster rate as the amount of oxygen increases within the channel layer, implying that the conventional VO‐related defect model is inappropriate in elucidating the PBS and NBIS instabilities of commercial SA‐TG coplanar IGZO TFTs, where the channel layers are formed under high oxygen flow rates (OFRs) to make VTH positive. On the basis of the full‐energy range subgap density of states extracted before and after each stress from IGZO TFTs with different OFRs, it is determined that the generation and annihilation of the subgap states in the excess oxygen peroxide configuration are the dominant physical mechanisms for PBS and NBIS instabilities in commercial SA‐TG coplanar IGZO TFTs, respectively.
We developed the novel TFT backplane structure on glass for ultra‐high resolution (1443 ppi) AMOLED VR display. The Mixed TFT backplane based on the combination of bottom‐gate poly‐Si TFTs (BGPs) and top‐gate poly‐Si TFTs (TGPs) has solved many issues such as integrating AMOLED pixel circuit in very small area and retaining TFT characteristics on glass for AMOLED VR display.
To improve the transmittance in IPS mode, submicron pixel electrodes were developed by new patterning process and structure. Unlike typical horizontal electrode structure, the electrodes are vertically formed on the sidewall with our new process. As a simulation result, these submicron electrodes improved transmittance about 10% than conventional type. With this new process, 15-inch panel was successfully fabricated..
/ J.-Y. Yang
SID 2012 DIGEST • 877
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