Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermomechanical reliability has to be assured. Dedicated stress tests have to be conducted to evaluate lifetime under relevant testing conditions, then failure mechanisms have to be identified, understood and quantitatively condensed into a lifetime model to predict reliability for future designs. In order to assure a short time to market, accelerated tests (and corresponding acceleration factors) are urgently needed by industry and are the holy grail of reliability as an academic discipline. The idea presented in this paper is to substitute lengthy thermal cycling tests by results obtained by rapi d isothermal fatigue tests at different temperatures and establish a correlation between both of them. Based on physics of failure principles, the applicability and viability of such a concept then is evaluated and discussed.In conclusion, this work shows a consistent approach for acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the TEVs. More data is needed to confirm the failure mechanisms in TEVs, reproducible samples for thermal cycling and to validate the applicability of the method also to other metal layers used in the electronic packaging industry

Finite Element Simulations of highly integrated and large electronics packages with detailed elastic-plastic material modeling of thousands of solder balls are still challenging tasks for today's computation systems. The complex geometry and mesh and the usage of time consuming creep laws for solder materials makes it nearly impossible to calculate different geometries or process parameters. This paper describes a method to reduce the complexity of the mesh in the region of the solder balls and surrounding underfill with one simple block physically described as a viscoelastic material. Therefore a viscoelastic/plastic behavior of a complex unit cell was modeled in a temperature dependent harmonic frequency sweep or relaxation simulation. The reaction of the unit cell was utilized to synthesize the master curve, Prony coefficients and shift function to an effective material model. Finally an error estimation of the unit cell approach was carried out

To satisfy the increasing need in today's industry for high performance, more complex chips are being designed. These chips, when integrated in 3D packages, have a high energy density and require new and innovative cooling strategies as many of them are designed as flip-chip assemblies, usually requiring back-side cooling. Classical underfills currently used offer poor thermal conductivity. But cooling through the underfill would enable cost-efficient and low complexity cooling solutions. For this purpose, thermal underfills with percolating fillers and necks are currently under development. They are to provide a significant improvement in thermal conductivity to classical capillary underfills and will find applications in, for example, 3D integrated packages to improve heat dissipation. The idea behind the percolating thermal underfill (PTU) comprises a sequential joint forming process ensuring a high fill fraction. Although flip chip technology has been well described, the addition of the neck based percolating underfill could entail several new thermo-mechanical reliability concerns that need to be studied using a physics of failure approach, since the PTU exhibits vastly different thermo-mechanical behavior, giving rise to possible new failure mechanisms and locations. This paper in particular deals with FE simulations carried out to understand different key aspects of the thermal underfill and to study the effects of the increased underfill stiffness at these locations. The simulations are implemented using detailed elastic, plastic, visco-elastic and visco-plastic material data. In case of larger models a complexity reduction is required and implemented by using effective material data to improve computational time

Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m-K)

Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermo-mechanical reliability has to be assured. Dedicated stress tests have to be conducted to evaluate lifetime under relevant testing conditions, then failure mechanisms have to be identified, understood and quantitatively condensed into a lifetime model to predict reliability for future designs. In order to assure a short time to market, accelerated tests (and corresponding acceleration factors) are urgently needed by industry and are the holy grail of reliability as an academic discipline. The idea presented in this paper is to substitute lengthy thermal cycling tests by results obtained by rapid isothe rmal fatigue tests at different temperatures and establish a correlation between both of them. Based on physics of failure principles, the applicability and viability of such a concept thenis evaluated and discussed. In conclusion, this work shows a consistent approach for acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the TEVs. More data is needed to confirm the failure mechanisms in TEVs, reproducible samples for thermal cycling and to validate the applicability of the method also to other metal layers used in the electronic packaging industry