No abstract

CMOS technology for 1.2V high performance applications is being scaled to sub-0.09pm physical nominal gate lengths and with effective gate dielectric thickness less than 2nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09pm (post gate reoxidation), and gate dielectric thickness of 2.7nm (nMOS), 3.0nm (PMOS) (inversion at 1.2V), nMOS and PMOS Idrive is 763 pA/pm and 333 pA/pm respectively, at 1.2V with maximum Ioff=5nA/pm. Gate-drain overlap in this work is -2 10 h i d e and bottomwall junction capacitance is reduced to 0.8 fF/pm2 (PMOS) and 1.1 fF/Fm2 (nMOS). With reduced parasitics and high drive current, the 1.2V technology FOM (Figure-of-Merit) is > 39GHz, meeting the roadmap trend.

An 86% electron mobility improvement and over 20% bm.,a, enhancement were demonstrated for a 70nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained8i process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage through a 16A nitrided oxide, which remained the dominant leakage source despite dislocation-induced junction leakage observed on strained-Si wafen. Self-heating of strained3 CMOS due to the low thermal conductivity SiGe virtual substrate reduces Id..,., by 7% during DC operation.

No abstract

High Idst enhancement is benefited from novel strained-Si process. However, it might cause reliability problems. Here we revealed the HCI degradation of strained-Si devices, which also can he correlated to I&, were worse than conventional bulk Si devices. Besides, it had high positive temperature coefficient in low voltages. Thus, it would be even worse at the operation voltage. [Keywords: hot carrier degradation, strained-Si, short channel.]