In this paper, some aspects of the electrical characterization of trapping phenomena occurring at interfaces between insulators and wide band semiconductors (WBG) are presented, with a focus on the SiO 2 /SiC and SiO 2 /GaN systems. In particular, time resolved capacitance, current measurements, and parallel conductance measurements as a function of frequency were correlated to investigate trapping states in SiC and GaN MOSstructures, allowing to distinguish between slow and fast states in these systems. Furthermore, gate current measurements enabled us to get insights into the near interface traps (NITs) present inside the SiO 2 layer. Evidently, in these systems, although postoxide deposition annealing treatments can reduce the interface traps (down to the 10 11 -10 12 cm À2 eV À1 range), the presence of the NITs is responsible for an anomalous behavior of the current conduction, penalizing the threshold voltage stability. Timedependent current and conductance measurements, performed in appropriate bias ranges, enabled to determine the density of NITs (1 Â 10 11 cm À2 ). The impact of the observed trapping phenomena on the SiO 2 /SiC(GaN) transistor operation is briefly discussed.