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We have developed 65nmnode CMOS technology for generalpurpose systemdnaship (SoC), in which both standby and active power reductions are strongly required. With highly reliable triple gate oxide ( 1 . 3~ 1.6nm and 3.2nm) using low damage process, an average standby current can be reduced to one-fifth compared with conventional case. Gate predoping and RTA conditions were optimized to maintain oniurrent even with the supply voltage of 0.9V. Highspeed (HS) transistors show on-currcnt of 6 8 0 p N~m for nFET and 240pNpm for pFET with 5 of 13nA/pm and I , , = of 30nAipm. Low-gateieakage (LGL) transistors show on-current of 490pNpm for nFET and 1 7 5~N p m for pFET with 5 of 0 . 8 N p m and Io= of 3nA/pm. Gate oxide of all the above transistors exhibit tight TDDB distributions.

In accordance with decrease of device size, ultra shallow junctions are required for realizing superior device performance. Enhanced diffusion caused by implantation is a crucial factor to realize ultra shallow junctions. Not only implant but also RTA conditions are key factors to suppress enhanced diffusion. In this paper, process conditions to minimize enhanced diffusion are discussed. Implant ion species, energy, dose and beam current parameters are investigated for implantation and temperature, time and ramping rate parameters are investigated for RTA. Important result is that optimization of not only implant but also RTA conditions should be carried out in order to fabricate ultra shallow junctions.

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